summaryrefslogtreecommitdiff
path: root/drivers/clk/renesas
AgeCommit message (Expand)Author
2023-12-13clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1Claudiu Beznea
2023-12-13clk: renesas: rzg2l: Check reset monitor registersClaudiu Beznea
2023-12-13clk: renesas: r9a08g045: Add IA55 pclk and its resetClaudiu Beznea
2023-11-27clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()Claudiu Beznea
2023-11-20clk: renesas: r8a779g0: Add PCIe clocksYoshihiro Shimoda
2023-11-20clk: renesas: r8a779g0: Add EtherTSN clockNiklas Söderlund
2023-10-12clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2Claudiu Beznea
2023-10-12clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()Claudiu Beznea
2023-10-10clk: renesas: Add minimal boot support for RZ/G3S SoCClaudiu Beznea
2023-10-10clk: renesas: rzg2l: Add divider clock for RZ/G3SClaudiu Beznea
2023-10-10clk: renesas: rzg2l: Refactor SD mux driverClaudiu Beznea
2023-10-05clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic headerClaudiu Beznea
2023-10-05clk: renesas: rzg2l: Add struct clk_hw_dataClaudiu Beznea
2023-10-05clk: renesas: rzg2l: Add support for RZ/G3S PLLClaudiu Beznea
2023-10-05clk: renesas: rzg2l: Remove critical areaClaudiu Beznea
2023-10-05clk: renesas: rzg2l: Fix computation formulaClaudiu Beznea
2023-10-05clk: renesas: rzg2l: Trust value returned by hardwareClaudiu Beznea
2023-10-05clk: renesas: rzg2l: Lock around writes to mux registerClaudiu Beznea
2023-10-05clk: renesas: rzg2l: Wait for status bit of SD mux before continuingClaudiu Beznea
2023-10-05clk: renesas: rcar-gen3: Extend SDnH divider tableDirk Behme
2023-09-26clk: renesas: r8a7795: Constify r8a7795_*_clksMarek Vasut
2023-09-18clk: renesas: r9a06g032: Name anonymous structsRalph Siemsen
2023-09-18clk: renesas: r9a06g032: Fix kerneldoc warningRalph Siemsen
2023-09-18clk: renesas: rzg2l: Use u32 for flag and mux_flagsClaudiu Beznea
2023-09-18clk: renesas: rzg2l: Use FIELD_GET() for PLL register fieldsClaudiu Beznea
2023-09-18clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()Claudiu Beznea
2023-09-18clk: renesas: rzg2l: Use core->name for clock nameClaudiu Beznea
2023-09-11clk: renesas: r9a06g032: Use for_each_compatible_node()Yang Yingliang
2023-08-30Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'c...Stephen Boyd
2023-08-15clk: renesas: rcar-gen3: Add ADG clocksKuninori Morimoto
2023-07-27clk: renesas: r8a77965: Add 3DGE and ZG supportGeert Uytterhoeven
2023-07-27clk: renesas: r8a7796: Add 3DGE and ZG supportGeert Uytterhoeven
2023-07-27clk: renesas: r8a7795: Add 3DGE and ZG supportGeert Uytterhoeven
2023-07-27clk: renesas: emev2: Remove obsolete clkdev registrationGeert Uytterhoeven
2023-07-25clk: renesas: r9a07g043: Add MTU3a clock and reset entryBiju Das
2023-07-19clk: Explicitly include correct DT includesRob Herring
2023-07-11clk: renesas: rzg2l: Simplify .determine_rate()Christophe JAILLET
2023-07-10clk: renesas: r9a09g011: Add CSI related clocksFabrizio Castro
2023-07-10clk: renesas: r8a774b1: Add 3DGE and ZG supportAdam Ford
2023-07-10clk: renesas: r8a774e1: Add 3DGE and ZG supportAdam Ford
2023-07-10clk: renesas: r8a774a1: Add 3DGE and ZG supportAdam Ford
2023-07-10clk: renesas: rcar-gen3: Add support for ZG clockAdam Ford
2023-06-26Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-sam...Stephen Boyd
2023-06-08clk: renesas: r9a06g032: Add a determine_rate hookMaxime Ripard
2023-06-05clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven
2023-06-05clk: renesas: mstp: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven
2023-06-05clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven
2023-05-23clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register writeBiju Das
2023-05-08clk: renesas: r8a779a0: Add PWM clockWolfram Sang
2023-04-29Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds