diff options
| author | Adam Ford <aford173@gmail.com> | 2023-06-17 10:03:00 -0500 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-07-10 09:31:29 +0200 |
| commit | f7b0dfffd3e0897ca73916a0c3d3fb61c61df51e (patch) | |
| tree | f01e5355d583215f6aac98d21261195319a3fb4d /drivers/clk/renesas | |
| parent | 1bc6f6dda0a3158af0703110656273958793f076 (diff) | |
clk: renesas: r8a774a1: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230617150302.38477-2-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a774a1-cpg-mssr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index ad03c09ebc1f..7e70c9a9affa 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), + DEF_GEN3_Z("zg", R8A774A1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -123,6 +124,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { + DEF_MOD("3dge", 112, R8A774A1_CLK_ZG), DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6), DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2), DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2), |