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2024-06-23arm64: dts: qcom: sa8775p: add a dedicated memory carveout for TZBartosz Golaszewski
Add a 20MB reserved memory region for use by SCM calls. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240527-shm-bridge-v10-15-ce7afaa58d3a@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sa8775p-*: Remove thermal zone polling delaysKonrad Dybcio
All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-15-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06Merge branch 'arm64-fixes-for-6.10' into arm64-for-6.11Bjorn Andersson
Merge the arm64-fixes-for-6.10 branch into arm64-for-6.11 to resolve the merge conflict caused by pmic-glink and reserved-memory introduction at the same place in the x1e80100 crd and qcp dts files.
2024-06-04arm64: dts: qcom: sa8775p: Correct IRQ number of EL2 non-secure physical timerCong Zhang
The INTID of EL2 non-secure physical timer is 26. In linux, the IRQ number has a fixed 16 offset for PPIs. Therefore, the linux IRQ number of EL2 non-secure physical timer should be 10 (26 - 16). Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride") Signed-off-by: Cong Zhang <quic_congzhan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20240604085929.49227-1-quic_congzhan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-31arm64: dts: qcom: sa8775p: Add IMEM and PIL info regionTengfei Fan
Add a simple-mfd representing IMEM on SA8775p and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com> Link: https://lore.kernel.org/r/20240531093531.238075-3-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-29arm64: dts: qcom: sa8775p: Add llcc support for the SA8775p platformTengfei Fan
Add llcc support for the SA8775p platform. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Link: https://lore.kernel.org/r/20240529101534.3166507-4-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-28arm64: dts: qcom: sa8775p: mark ethernet devices as DMA-coherentSagar Cheluvegowda
Ethernet devices are cache coherent, mark it as such in the dtsi. Fixes: ff499a0fbb23 ("arm64: dts: qcom: sa8775p: add the first 1Gb ethernet interface") Fixes: e952348a7cc7 ("arm64: dts: qcom: sa8775p: add a node for EMAC1") Signed-off-by: Sagar Cheluvegowda <quic_scheluve@quicinc.com> Link: https://lore.kernel.org/r/20240514-mark_ethernet_devices_dma_coherent-v4-1-04e1198858c5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-27arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherentMrinmay Sarkar
The PCIe EP controller on SA8775P supports cache coherency, hence add the "dma-coherent" property to mark it as such. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1710166298-27144-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-27arm64: dts: qcom: Add coresight nodes for SA8775pJie Gan
Add following coresight components on SA8775p, TMC/ETF, TPDM, dynamic Funnel, TPDA and ETM. Signed-off-by: Jie Gan <quic_jiegan@quicinc.com> Link: https://lore.kernel.org/r/20240521011946.3148712-2-quic_jiegan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sa8775p: Add ep pcie1 controller nodeMrinmay Sarkar
Add ep pcie dtsi node for pcie1 controller found on sa8775p platform. It supports gen4 and x4 link width. Limiting the speed to Gen3 due to stability issue with Gen4. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1714494089-7917-3-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sa8775p: Add ep pcie0 controller nodeMrinmay Sarkar
Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. It supports gen4 and x2 link width. Limiting the speed to Gen3 due to stability issues. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1714492540-15419-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sa8775p: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-8-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sa8775p: Add new memory map updates to SA8775PNinad Naik
New memory map layout changes (by Qualcomm firmware) have brought in updates to base addresses and/or size for different memory regions like cpcucp_fw, tz-stat, and also introduces new memory regions for resource manager firmware. The updated memory map also fixes existing issues pertaining to boot up failure while running memtest, thus improving stability. This change brings in these corresponding memory map updates to the device tree for SA8775P SoC platform, which currently is in its development stage. Signed-off-by: Ninad Naik <quic_ninanaik@quicinc.com> Tested-by: Eric Chanudet <echanude@redhat.com> # sa8775p-ride Link: https://lore.kernel.org/r/20240125055134.7015-1-quic_ninanaik@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28arm64: dts: qcom: sa8775p: enable safety IRQSuraj Jaiswal
Add changes to support safety IRQ handling support for ethernet. Signed-off-by: Suraj Jaiswal <quic_jsuraj@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240110111649.2256450-3-quic_jsuraj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-27arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targetsKrishna Kurapati
On non-QUSB2 targets (like the ones that use femto phys, M31 phy, eusb2 phy), many of the QCOM DTs are missing the IRQ for either hs_phy_irq or pwr_event. In one case, the hs_phy_irq was incorrectly defined with the latter's IRQ number. Since the DT must describe the hw whether or not the driver uses these interrupts, fix and add the missing entries in order to describe the HW completely and accurately. Also modify order of interrupts in accordance to bindings update. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Link: https://lore.kernel.org/r/20240125185921.5062-3-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: sa8775p: Add missing space between node name and bracesManivannan Sadhasivam
Add missing space between node name and braces to match the style. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20231206135540.17068-4-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: Use "pcie" as the node name instead of "pci"Manivannan Sadhasivam
Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct node name for the controller instances. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20231206135540.17068-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07arm64: dts: qcom: sa8775p: fix USB wakeup interrupt typesJohan Hovold
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Note that only triggering on rising edges can be used to detect resume events but not disconnect events. Fixes: de1001525c1a ("arm64: dts: qcom: sa8775p: add USB nodes") Cc: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20231120164331.8116-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-02arm64: dts: qcom: sa8775p: Make watchdog bark interrupt edge triggeredDouglas Anderson
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered"), the Qualcomm watchdog timer's bark interrupt should be configured as edge triggered. Make the change. Fixes: 09b701b89a76 ("arm64: dts: qcom: sa8775p: add the watchdog node") Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20231106144335.v2.6.I909b7c4453d7b7fb0db4b6e49aa21666279d827d@changeid Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-10-16arm64: dts: qcom: Enable tsens and thermal for sa8775p SoCPriyansh Jain
Add tsens and thermal devicetree node for sa8775p SoC. Signed-off-by: Priyansh Jain <quic_priyjain@quicinc.com> Link: https://lore.kernel.org/r/20230926085948.23046-3-quic_priyjain@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-10-16arm64: dts: qcom: sa8775p: Add RPMh sleep statsRaghavendra Kakarla
Add device node for sleep stats driver which provides various low power mode stats. Tested-by: Andrew Halaney <ahalaney@redhat.com> Signed-off-by: Raghavendra Kakarla <quic_rkakarla@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230929054805.27847-1-quic_rkakarla@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-10-15arm64: dts: qcom: sa8775p: add TRNG nodeOm Prakash Singh
The sa8775p SoC has a True Random Number Generator, add the node with the correct compatible set. Signed-off-by: Om Prakash Singh <quic_omprsing@quicinc.com> Link: https://lore.kernel.org/r/20231015193901.2344590-4-quic_omprsing@quicinc.com [bjorn: Padded address to 8 digits, moved hunk to maintain sort order] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-20arm64: dts: qcom: sa8775p: enable the inline crypto engineBartosz Golaszewski
Add an ICE node to sa8775p SoC description and enable it by adding a phandle to the UFS node. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230913153529.32777-2-bartosz.golaszewski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-15arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMMKonrad Dybcio
Some TLMM pins are wakeup-capable. Describe the relationship between these two peripherals to enable this functionality. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230811-topic-tlmm_wakeup-v1-4-5616a7da1fff@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-11arm64: dts: qcom: sa8775p: add a node for EMAC1Bartosz Golaszewski
Add a node for the second MAC on sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230810080909.6259-3-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-11arm64: dts: qcom: sa8775p: add a node for the second serdes PHYBartosz Golaszewski
Add a node for the SerDes PHY used by EMAC1 on sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230810080909.6259-2-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-21arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodesMrinmay Sarkar
Add pcie dtsi nodes for two controllers found on sa8775p platform. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1689960276-29266-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: sa8775p: add the first 1Gb ethernet interfaceBartosz Golaszewski
Add the node for the first ethernet interface on sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230622120142.218055-3-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: sa8775p: add the SGMII PHY nodeBartosz Golaszewski
Add the internal SGMII/SerDes PHY node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230622120142.218055-2-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-06-29Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM SoC devicetree updates from Arnd Bergmann: "The biggest change this time is for the 32-bit devicetree files, which are all moved to a new location, using separate subdirectories for each SoC vendor, following the same scheme that is used on arm64, mips and riscv. This has been discussed for many years, but so far we never did this as there was a plan to move the files out of the kernel entirely, which has never happened. The impact of this will be that all external patches no longer apply, and anything depending on the location of the dtb files in the build directory will have to change. The installed files after 'make dtbs_install' keep the current location. There are six added SoCs here that are largely variants of previously added chips. Two other chips are added in a separate branch along with their device drivers. - The Samsung Exynos 4212 makes its return after the Samsung Galaxy Express phone is addded at last. The SoC support was originally added in 2012 but removed again in 2017 as it was unused at the time. - Amlogic C3 is a Cortex-A35 based smart IP camera chip - Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of the still common MSM8916 (Snapdragon 410) phone chip that has been supported for a long time. - Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end laptop chips, used in the Lenovo Flex 5G, which is added along with the reference board. - Qualcomm SDX75 is the latest generation modem chip that is used as a peripherial in phones but can also run a standalone Linux. Unlike the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55. - Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie C910 core, a step up from all previously added rv64 chips. All of the above come with reference board implementations, those included there are 39 new board files, but only five more 32-bit this time, probably a new low: - Marantec Maveo board based on dhcor imx6ull module - Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip - Epson Moverio BT-200 AR glasses based on TI OMAP4 - PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM - ICnova ADB4006 board based on Allwinner A20 On the 64-bit side, there are also fewer addded machines than we had in the recent releases: - Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device. - NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234 - Qualcomm gains support for 6 reference boards on various members of their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top of the various reference platforms for their new chips. - Rockchips support for several newer boards: Indiedroid Nova (rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S (rk3568) - TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin family with AM62 COM, carrier and dev boards Other changes to existing boards contain the usual minor improvements along with - continued updates to clean up dts files based on dtc warnings and binding checks, in particular cache properties and node names - support for devicetree overlays on at91, bcm283x - significant additions to existing SoC support on mediatek, qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1 As usual, a lot more detail is available in the individual merge commits" * tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits) ARM: mvebu: fix unit address on armada-390-db flash ARM: dts: Move .dts files to vendor sub-directories kbuild: Support flat DTBs install ARM: dts: Add .dts files missing from the build ARM: dts: allwinner: Use quoted #include ARM: dts: lan966x: kontron-d10: add PHY interrupts ARM: dts: lan966x: kontron-d10: fix SPI CS ARM: dts: lan966x: kontron-d10: fix board reset ARM: dts: at91: Enable device-tree overlay support for AT91 boards arm: dts: Enable device-tree overlay support for AT91 boards arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller ARM: dts: at91: use generic name for shutdown controller ARM: dts: BCM5301X: Add cells sizes to PCIe nodes dt-bindings: firmware: brcm,kona-smc: convert to YAML riscv: dts: sort makefile entries by directory riscv: defconfig: enable T-HEAD SoC MAINTAINERS: add entry for T-HEAD RISC-V SoC riscv: dts: thead: add sipeed Lichee Pi 4A board device tree riscv: dts: add initial T-HEAD TH1520 SoC device tree riscv: Add the T-HEAD SoC family Kconfig option ...
2023-05-26arm64: dts: qcom: sa8775p: add uart5 and uart9 nodesShazad Hussain
Add remaining uart5 and uart9 nodes for UART bus present on sa8775p SoC. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-5-quic_shazhuss@quicinc.com
2023-05-26arm64: dts: qcom: sa8775p: add missing spi nodesShazad Hussain
Add the missing nodes of the SPI buses present on sa8775p platform. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-4-quic_shazhuss@quicinc.com
2023-05-26arm64: dts: qcom: sa8775p: add missing i2c nodesShazad Hussain
Add the missing nodes for the i2c buses present on sa8775p Soc. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-3-quic_shazhuss@quicinc.com
2023-05-26arm64: dts: qcom: sa8775p: add the QUPv3 #0 and #3 nodeShazad Hussain
Add zeroth and third instance of the QUPv3 engine to the sa8775p.dtsi. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-2-quic_shazhuss@quicinc.com
2023-05-17arm64: dts: qcom: add missing cache propertiesKrzysztof Kozlowski
Add required cache-level and cache-unified properties to fix warnings like: qdu1000-idp.dtb: l3-cache: 'cache-unified' is a required property qdu1000-idp.dtb: l2-cache: 'cache-level' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230416101134.95686-3-krzysztof.kozlowski@linaro.org
2023-05-17arm64: dts: qcom: sa8775p: mark the UFS controller as dma-coherentBartosz Golaszewski
The UFS controller is cache coherent, so mark it as such in the dtsi. Fixes: be543efeee17 ("arm64: dts: qcom: sa8775p: add UFS nodes") Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Suggested-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230515121908.303432-1-brgl@bgdev.pl
2023-05-14arm64: dts: qcom: sa8775p: enable AOSSBartosz Golaszewski
Enable the always-on subsystem controller on SA8775P platforms for use by upcoming support for other peripherals. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230504161755.197417-2-brgl@bgdev.pl
2023-05-14arm64: dts: qcom: sa8775p: add USB nodesShazad Hussain
Add nodes for the USB and it's PHY on sa8775p platform. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230428130824.23803-6-quic_shazhuss@quicinc.com
2023-05-14arm64: dts: qcom: sa8775p: add the watchdog nodeBartosz Golaszewski
Now that the hypervisor issue is fixed, we can add the watchdog node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230427161218.201828-1-brgl@bgdev.pl
2023-05-14arm64: dts: qcom: sa8775p: add the GPU IOMMU nodeBartosz Golaszewski
Add the Adreno GPU IOMMU for sa8775p-based platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417125844.400782-6-brgl@bgdev.pl
2023-05-14arm64: dts: qcom: sa8775p: add the GPU clock controller nodeBartosz Golaszewski
Add the GPUCC node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417125844.400782-4-brgl@bgdev.pl
2023-05-14arm64: dts: qcom: sa8775p: add the pcie smmu nodeBartosz Golaszewski
Add the PCIe SMMU node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417125844.400782-3-brgl@bgdev.pl
2023-05-14arm64: dts: qcom: sa8775p: add UFS nodesBartosz Golaszewski
Add nodes for the UFS and its PHY on sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230411130446.401440-5-brgl@bgdev.pl
2023-05-14arm64: dts: qcom: sa8775p: add the PMU nodeBartosz Golaszewski
Add the PMU node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230414123016.176457-1-brgl@bgdev.pl
2023-04-04arm64: dts: qcom: sa8775p: add the spmi nodeBartosz Golaszewski
Add the SPMI PMIC Arbiter node for SA8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327125316.210812-6-brgl@bgdev.pl
2023-04-04arm64: dts: qcom: sa8775p: add the pdc nodeBartosz Golaszewski
Add the Power Domain Controller node for SA8775p. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327125316.210812-5-brgl@bgdev.pl
2023-04-04arm64: dts: qcom: sa8775p: sort soc nodes by reg propertyBartosz Golaszewski
Sort all children of the soc node by the first address in their reg property. This was mostly already the case but there were some nodes that didn't follow it so fix it now for consistency. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327125316.210812-3-brgl@bgdev.pl
2023-04-04arm64: dts: qcom: sa8775p: pad reg properties to 8 digitsBartosz Golaszewski
The file has inconsistent padding of the address part of soc node children's reg properties. Fix it. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327125316.210812-2-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: sa8775p: add high-speed UART nodesBartosz Golaszewski
Add two UART nodes that are known to be used by existing development boards with this SoC. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-8-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: sa8775p: add the spi16 nodeBartosz Golaszewski
Add the SPI controller node for the interface exposed on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-6-brgl@bgdev.pl
generated by cgit v1.2.3-58-ga151 (git 2.39.0) at 2024-12-18 06:42:43 +0000