summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
blob: b6e4df180f0b0a6289d1dc5584659392239c9799 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
 */

#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/ata/ahci.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "rockchip,rk3588";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		gpio4 = &gpio4;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		i2c8 = &i2c8;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &uart6;
		serial7 = &uart7;
		serial8 = &uart8;
		serial9 = &uart9;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		spi4 = &spi4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu_l0>;
				};
				core1 {
					cpu = <&cpu_l1>;
				};
				core2 {
					cpu = <&cpu_l2>;
				};
				core3 {
					cpu = <&cpu_l3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu_b0>;
				};
				core1 {
					cpu = <&cpu_b1>;
				};
			};
			cluster2 {
				core0 {
					cpu = <&cpu_b2>;
				};
				core1 {
					cpu = <&cpu_b3>;
				};
			};
		};

		cpu_l0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0>;
			enable-method = "psci";
			capacity-dmips-mhz = <530>;
			clocks = <&scmi_clk SCMI_CLK_CPUL>;
			assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
			assigned-clock-rates = <816000000>;
			cpu-idle-states = <&CPU_SLEEP>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l0>;
			dynamic-power-coefficient = <228>;
			#cooling-cells = <2>;
		};

		cpu_l1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <530>;
			clocks = <&scmi_clk SCMI_CLK_CPUL>;
			cpu-idle-states = <&CPU_SLEEP>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l1>;
			dynamic-power-coefficient = <228>;
			#cooling-cells = <2>;
		};

		cpu_l2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x200>;
			enable-method = "psci";
			capacity-dmips-mhz = <530>;
			clocks = <&scmi_clk SCMI_CLK_CPUL>;
			cpu-idle-states = <&CPU_SLEEP>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l2>;
			dynamic-power-coefficient = <228>;
			#cooling-cells = <2>;
		};

		cpu_l3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x300>;
			enable-method = "psci";
			capacity-dmips-mhz = <530>;
			clocks = <&scmi_clk SCMI_CLK_CPUL>;
			cpu-idle-states = <&CPU_SLEEP>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l3>;
			dynamic-power-coefficient = <228>;
			#cooling-cells = <2>;
		};

		cpu_b0: cpu@400 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x400>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
			assigned-clock-rates = <816000000>;
			cpu-idle-states = <&CPU_SLEEP>;
			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_cache_b0>;
			dynamic-power-coefficient = <416>;
			#cooling-cells = <2>;
		};

		cpu_b1: cpu@500 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x500>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
			cpu-idle-states = <&CPU_SLEEP>;
			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_cache_b1>;
			dynamic-power-coefficient = <416>;
			#cooling-cells = <2>;
		};

		cpu_b2: cpu@600 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x600>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
			assigned-clock-rates = <816000000>;
			cpu-idle-states = <&CPU_SLEEP>;
			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_cache_b2>;
			dynamic-power-coefficient = <416>;
			#cooling-cells = <2>;
		};

		cpu_b3: cpu@700 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x700>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
			cpu-idle-states = <&CPU_SLEEP>;
			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_cache_b3>;
			dynamic-power-coefficient = <416>;
			#cooling-cells = <2>;
		};

		idle-states {
			entry-method = "psci";
			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <100>;
				exit-latency-us = <120>;
				min-residency-us = <1000>;
			};
		};

		l2_cache_l0: l2-cache-l0 {
			compatible = "cache";
			cache-size = <131072>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_l1: l2-cache-l1 {
			compatible = "cache";
			cache-size = <131072>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_l2: l2-cache-l2 {
			compatible = "cache";
			cache-size = <131072>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_l3: l2-cache-l3 {
			compatible = "cache";
			cache-size = <131072>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_b0: l2-cache-b0 {
			compatible = "cache";
			cache-size = <524288>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_b1: l2-cache-b1 {
			compatible = "cache";
			cache-size = <524288>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_b2: l2-cache-b2 {
			compatible = "cache";
			cache-size = <524288>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_b3: l2-cache-b3 {
			compatible = "cache";
			cache-size = <524288>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l3_cache: l3-cache {
			compatible = "cache";
			cache-size = <3145728>;
			cache-line-size = <64>;
			cache-sets = <4096>;
			cache-level = <3>;
			cache-unified;
		};
	};

	display_subsystem: display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <&vop_out>;
	};

	firmware {
		optee: optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		scmi: scmi {
			compatible = "arm,scmi-smc";
			arm,smc-id = <0x82000010>;
			shmem = <&scmi_shmem>;
			#address-cells = <1>;
			#size-cells = <0>;

			scmi_clk: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};

			scmi_reset: protocol@16 {
				reg = <0x16>;
				#reset-cells = <1>;
			};
		};
	};

	pmu-a55 {
		compatible = "arm,cortex-a55-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
	};

	pmu-a76 {
		compatible = "arm,cortex-a76-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	spll: clock-0 {
		compatible = "fixed-clock";
		clock-frequency = <702000000>;
		clock-output-names = "spll";
		#clock-cells = <0>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
	};

	xin24m: clock-1 {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	xin32k: clock-2 {
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "xin32k";
		#clock-cells = <0>;
	};

	pmu_sram: sram@10f000 {
		compatible = "mmio-sram";
		reg = <0x0 0x0010f000 0x0 0x100>;
		ranges = <0 0x0 0x0010f000 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;

		scmi_shmem: sram@0 {
			compatible = "arm,scmi-shmem";
			reg = <0x0 0x100>;
		};
	};

	gpu: gpu@fb000000 {
		compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
		reg = <0x0 0xfb000000 0x0 0x200000>;
		#cooling-cells = <2>;
		assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
		assigned-clock-rates = <200000000>;
		clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
			 <&cru CLK_GPU_STACKS>;
		clock-names = "core", "coregroup", "stacks";
		dynamic-power-coefficient = <2982>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "job", "mmu", "gpu";
		power-domains = <&power RK3588_PD_GPU>;
		status = "disabled";
	};

	usb_host0_xhci: usb@fc000000 {
		compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
		reg = <0x0 0xfc000000 0x0 0x400000>;
		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
			 <&cru ACLK_USB3OTG0>;
		clock-names = "ref_clk", "suspend_clk", "bus_clk";
		dr_mode = "otg";
		phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
		phy-names = "usb2-phy", "usb3-phy";
		phy_type = "utmi_wide";
		power-domains = <&power RK3588_PD_USB>;
		resets = <&cru SRST_A_USB3OTG0>;
		snps,dis_enblslpm_quirk;
		snps,dis-u1-entry-quirk;
		snps,dis-u2-entry-quirk;
		snps,dis-u2-freeclk-exists-quirk;
		snps,dis-del-phy-power-chg-quirk;
		snps,dis-tx-ipgap-linecheck-quirk;
		status = "disabled";
	};

	usb_host0_ehci: usb@fc800000 {
		compatible = "rockchip,rk3588-ehci", "generic-ehci";
		reg = <0x0 0xfc800000 0x0 0x40000>;
		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
		phys = <&u2phy2_host>;
		phy-names = "usb";
		power-domains = <&power RK3588_PD_USB>;
		status = "disabled";
	};

	usb_host0_ohci: usb@fc840000 {
		compatible = "rockchip,rk3588-ohci", "generic-ohci";
		reg = <0x0 0xfc840000 0x0 0x40000>;
		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
		phys = <&u2phy2_host>;
		phy-names = "usb";
		power-domains = <&power RK3588_PD_USB>;
		status = "disabled";
	};

	usb_host1_ehci: usb@fc880000 {
		compatible = "rockchip,rk3588-ehci", "generic-ehci";
		reg = <0x0 0xfc880000 0x0 0x40000>;
		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
		phys = <&u2phy3_host>;
		phy-names = "usb";
		power-domains = <&power RK3588_PD_USB>;
		status = "disabled";
	};

	usb_host1_ohci: usb@fc8c0000 {
		compatible = "rockchip,rk3588-ohci", "generic-ohci";
		reg = <0x0 0xfc8c0000 0x0 0x40000>;
		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
		phys = <&u2phy3_host>;
		phy-names = "usb";
		power-domains = <&power RK3588_PD_USB>;
		status = "disabled";
	};

	usb_host2_xhci: usb@fcd00000 {
		compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
		reg = <0x0 0xfcd00000 0x0 0x400000>;
		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
			 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
			 <&cru CLK_PIPEPHY2_PIPE_U3_G>;
		clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
		dr_mode = "host";
		phys = <&combphy2_psu PHY_TYPE_USB3>;
		phy-names = "usb3-phy";
		phy_type = "utmi_wide";
		resets = <&cru SRST_A_USB3OTG2>;
		snps,dis_enblslpm_quirk;
		snps,dis-u2-freeclk-exists-quirk;
		snps,dis-del-phy-power-chg-quirk;
		snps,dis-tx-ipgap-linecheck-quirk;
		snps,dis_rxdet_inp3_quirk;
		status = "disabled";
	};

	mmu600_pcie: iommu@fc900000 {
		compatible = "arm,smmu-v3";
		reg = <0x0 0xfc900000 0x0 0x200000>;
		interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
		#iommu-cells = <1>;
		status = "disabled";
	};

	mmu600_php: iommu@fcb00000 {
		compatible = "arm,smmu-v3";
		reg = <0x0 0xfcb00000 0x0 0x200000>;
		interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
		#iommu-cells = <1>;
		status = "disabled";
	};

	pmu1grf: syscon@fd58a000 {
		compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
		reg = <0x0 0xfd58a000 0x0 0x10000>;
	};

	sys_grf: syscon@fd58c000 {
		compatible = "rockchip,rk3588-sys-grf", "syscon";
		reg = <0x0 0xfd58c000 0x0 0x1000>;
	};

	vop_grf: syscon@fd5a4000 {
		compatible = "rockchip,rk3588-vop-grf", "syscon";
		reg = <0x0 0xfd5a4000 0x0 0x2000>;
	};

	vo0_grf: syscon@fd5a6000 {
		compatible = "rockchip,rk3588-vo-grf", "syscon";
		reg = <0x0 0xfd5a6000 0x0 0x2000>;
		clocks = <&cru PCLK_VO0GRF>;
	};

	vo1_grf: syscon@fd5a8000 {
		compatible = "rockchip,rk3588-vo-grf", "syscon";
		reg = <0x0 0xfd5a8000 0x0 0x100>;
		clocks = <&cru PCLK_VO1GRF>;
	};

	usb_grf: syscon@fd5ac000 {
		compatible = "rockchip,rk3588-usb-grf", "syscon";
		reg = <0x0 0xfd5ac000 0x0 0x4000>;
	};

	php_grf: syscon@fd5b0000 {
		compatible = "rockchip,rk3588-php-grf", "syscon";
		reg = <0x0 0xfd5b0000 0x0 0x1000>;
	};

	pipe_phy0_grf: syscon@fd5bc000 {
		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
		reg = <0x0 0xfd5bc000 0x0 0x100>;
	};

	pipe_phy2_grf: syscon@fd5c4000 {
		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
		reg = <0x0 0xfd5c4000 0x0 0x100>;
	};

	usbdpphy0_grf: syscon@fd5c8000 {
		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
		reg = <0x0 0xfd5c8000 0x0 0x4000>;
	};

	usb2phy0_grf: syscon@fd5d0000 {
		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
		reg = <0x0 0xfd5d0000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;

		u2phy0: usb2phy@0 {
			compatible = "rockchip,rk3588-usb2phy";
			reg = <0x0 0x10>;
			#clock-cells = <0>;
			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
			clock-names = "phyclk";
			clock-output-names = "usb480m_phy0";
			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
			resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
			reset-names = "phy", "apb";
			status = "disabled";

			u2phy0_otg: otg-port {
				#phy-cells = <0>;
				status = "disabled";
			};
		};
	};

	usb2phy2_grf: syscon@fd5d8000 {
		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
		reg = <0x0 0xfd5d8000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;

		u2phy2: usb2phy@8000 {
			compatible = "rockchip,rk3588-usb2phy";
			reg = <0x8000 0x10>;
			#clock-cells = <0>;
			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
			clock-names = "phyclk";
			clock-output-names = "usb480m_phy2";
			interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
			resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
			reset-names = "phy", "apb";
			status = "disabled";

			u2phy2_host: host-port {
				#phy-cells = <0>;
				status = "disabled";
			};
		};
	};

	usb2phy3_grf: syscon@fd5dc000 {
		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
		reg = <0x0 0xfd5dc000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;

		u2phy3: usb2phy@c000 {
			compatible = "rockchip,rk3588-usb2phy";
			reg = <0xc000 0x10>;
			#clock-cells = <0>;
			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
			clock-names = "phyclk";
			clock-output-names = "usb480m_phy3";
			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
			resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
			reset-names = "phy", "apb";
			status = "disabled";

			u2phy3_host: host-port {
				#phy-cells = <0>;
				status = "disabled";
			};
		};
	};

	hdptxphy0_grf: syscon@fd5e0000 {
		compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
		reg = <0x0 0xfd5e0000 0x0 0x100>;
	};

	ioc: syscon@fd5f0000 {
		compatible = "rockchip,rk3588-ioc", "syscon";
		reg = <0x0 0xfd5f0000 0x0 0x10000>;
	};

	system_sram1: sram@fd600000 {
		compatible = "mmio-sram";
		reg = <0x0 0xfd600000 0x0 0x100000>;
		ranges = <0x0 0x0 0xfd600000 0x100000>;
		#address-cells = <1>;
		#size-cells = <1>;
	};

	cru: clock-controller@fd7c0000 {
		compatible = "rockchip,rk3588-cru";
		reg = <0x0 0xfd7c0000 0x0 0x5c000>;
		assigned-clocks =
			<&cru PLL_PPLL>, <&cru PLL_AUPLL>,
			<&cru PLL_NPLL>, <&cru PLL_GPLL>,
			<&cru ACLK_CENTER_ROOT>,
			<&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
			<&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
			<&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
			<&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
			<&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
			<&cru CLK_GPU>;
		assigned-clock-rates =
			<1100000000>, <786432000>,
			<850000000>, <1188000000>,
			<702000000>,
			<400000000>, <500000000>,
			<800000000>, <100000000>,
			<400000000>, <100000000>,
			<200000000>, <500000000>,
			<375000000>, <150000000>,
			<200000000>;
		rockchip,grf = <&php_grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	i2c0: i2c@fd880000 {
		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
		reg = <0x0 0xfd880000 0x0 0x1000>;
		interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
		clock-names = "i2c", "pclk";
		pinctrl-0 = <&i2c0m0_xfer>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	uart0: serial@fd890000 {
		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfd890000 0x0 0x100>;
		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac0 6>, <&dmac0 7>;
		dma-names = "tx", "rx";
		pinctrl-0 = <&uart0m1_xfer>;
		pinctrl-names = "default";
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	pwm0: pwm@fd8b0000 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfd8b0000 0x0 0x10>;
		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm0m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm1: pwm@fd8b0010 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfd8b0010 0x0 0x10>;
		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm1m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm2: pwm@fd8b0020 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfd8b0020 0x0 0x10>;
		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm2m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm3: pwm@fd8b0030 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfd8b0030 0x0 0x10>;
		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm3m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pmu: power-management@fd8d8000 {
		compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
		reg = <0x0 0xfd8d8000 0x0 0x400>;

		power: power-controller {
			compatible = "rockchip,rk3588-power-controller";
			#address-cells = <1>;
			#power-domain-cells = <1>;
			#size-cells = <0>;
			status = "okay";

			/* These power domains are grouped by VD_NPU */
			power-domain@RK3588_PD_NPU {
				reg = <RK3588_PD_NPU>;
				#power-domain-cells = <0>;
				#address-cells = <1>;
				#size-cells = <0>;

				power-domain@RK3588_PD_NPUTOP {
					reg = <RK3588_PD_NPUTOP>;
					clocks = <&cru HCLK_NPU_ROOT>,
						 <&cru PCLK_NPU_ROOT>,
						 <&cru CLK_NPU_DSU0>,
						 <&cru HCLK_NPU_CM0_ROOT>;
					pm_qos = <&qos_npu0_mwr>,
						 <&qos_npu0_mro>,
						 <&qos_mcu_npu>;
					#power-domain-cells = <0>;
					#address-cells = <1>;
					#size-cells = <0>;

					power-domain@RK3588_PD_NPU1 {
						reg = <RK3588_PD_NPU1>;
						clocks = <&cru HCLK_NPU_ROOT>,
							 <&cru PCLK_NPU_ROOT>,
							 <&cru CLK_NPU_DSU0>;
						pm_qos = <&qos_npu1>;
						#power-domain-cells = <0>;
					};
					power-domain@RK3588_PD_NPU2 {
						reg = <RK3588_PD_NPU2>;
						clocks = <&cru HCLK_NPU_ROOT>,
							 <&cru PCLK_NPU_ROOT>,
							 <&cru CLK_NPU_DSU0>;
						pm_qos = <&qos_npu2>;
						#power-domain-cells = <0>;
					};
				};
			};
			/* These power domains are grouped by VD_GPU */
			power-domain@RK3588_PD_GPU {
				reg = <RK3588_PD_GPU>;
				clocks = <&cru CLK_GPU>,
					 <&cru CLK_GPU_COREGROUP>,
					 <&cru CLK_GPU_STACKS>;
				pm_qos = <&qos_gpu_m0>,
					 <&qos_gpu_m1>,
					 <&qos_gpu_m2>,
					 <&qos_gpu_m3>;
				#power-domain-cells = <0>;
			};
			/* These power domains are grouped by VD_VCODEC */
			power-domain@RK3588_PD_VCODEC {
				reg = <RK3588_PD_VCODEC>;
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <0>;

				power-domain@RK3588_PD_RKVDEC0 {
					reg = <RK3588_PD_RKVDEC0>;
					clocks = <&cru HCLK_RKVDEC0>,
						 <&cru HCLK_VDPU_ROOT>,
						 <&cru ACLK_VDPU_ROOT>,
						 <&cru ACLK_RKVDEC0>,
						 <&cru ACLK_RKVDEC_CCU>;
					pm_qos = <&qos_rkvdec0>;
					#power-domain-cells = <0>;
				};
				power-domain@RK3588_PD_RKVDEC1 {
					reg = <RK3588_PD_RKVDEC1>;
					clocks = <&cru HCLK_RKVDEC1>,
						 <&cru HCLK_VDPU_ROOT>,
						 <&cru ACLK_VDPU_ROOT>,
						 <&cru ACLK_RKVDEC1>;
					pm_qos = <&qos_rkvdec1>;
					#power-domain-cells = <0>;
				};
				power-domain@RK3588_PD_VENC0 {
					reg = <RK3588_PD_VENC0>;
					clocks = <&cru HCLK_RKVENC0>,
						 <&cru ACLK_RKVENC0>;
					pm_qos = <&qos_rkvenc0_m0ro>,
						 <&qos_rkvenc0_m1ro>,
						 <&qos_rkvenc0_m2wo>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					power-domain@RK3588_PD_VENC1 {
						reg = <RK3588_PD_VENC1>;
						clocks = <&cru HCLK_RKVENC1>,
							 <&cru HCLK_RKVENC0>,
							 <&cru ACLK_RKVENC0>,
							 <&cru ACLK_RKVENC1>;
						pm_qos = <&qos_rkvenc1_m0ro>,
							 <&qos_rkvenc1_m1ro>,
							 <&qos_rkvenc1_m2wo>;
						#power-domain-cells = <0>;
					};
				};
			};
			/* These power domains are grouped by VD_LOGIC */
			power-domain@RK3588_PD_VDPU {
				reg = <RK3588_PD_VDPU>;
				clocks = <&cru HCLK_VDPU_ROOT>,
					 <&cru ACLK_VDPU_LOW_ROOT>,
					 <&cru ACLK_VDPU_ROOT>,
					 <&cru ACLK_JPEG_DECODER_ROOT>,
					 <&cru ACLK_IEP2P0>,
					 <&cru HCLK_IEP2P0>,
					 <&cru ACLK_JPEG_ENCODER0>,
					 <&cru HCLK_JPEG_ENCODER0>,
					 <&cru ACLK_JPEG_ENCODER1>,
					 <&cru HCLK_JPEG_ENCODER1>,
					 <&cru ACLK_JPEG_ENCODER2>,
					 <&cru HCLK_JPEG_ENCODER2>,
					 <&cru ACLK_JPEG_ENCODER3>,
					 <&cru HCLK_JPEG_ENCODER3>,
					 <&cru ACLK_JPEG_DECODER>,
					 <&cru HCLK_JPEG_DECODER>,
					 <&cru ACLK_RGA2>,
					 <&cru HCLK_RGA2>;
				pm_qos = <&qos_iep>,
					 <&qos_jpeg_dec>,
					 <&qos_jpeg_enc0>,
					 <&qos_jpeg_enc1>,
					 <&qos_jpeg_enc2>,
					 <&qos_jpeg_enc3>,
					 <&qos_rga2_mro>,
					 <&qos_rga2_mwo>;
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <0>;


				power-domain@RK3588_PD_AV1 {
					reg = <RK3588_PD_AV1>;
					clocks = <&cru PCLK_AV1>,
						 <&cru ACLK_AV1>,
						 <&cru HCLK_VDPU_ROOT>;
					pm_qos = <&qos_av1>;
					#power-domain-cells = <0>;
				};
				power-domain@RK3588_PD_RKVDEC0 {
					reg = <RK3588_PD_RKVDEC0>;
					clocks = <&cru HCLK_RKVDEC0>,
						 <&cru HCLK_VDPU_ROOT>,
						 <&cru ACLK_VDPU_ROOT>,
						 <&cru ACLK_RKVDEC0>;
					pm_qos = <&qos_rkvdec0>;
					#power-domain-cells = <0>;
				};
				power-domain@RK3588_PD_RKVDEC1 {
					reg = <RK3588_PD_RKVDEC1>;
					clocks = <&cru HCLK_RKVDEC1>,
						 <&cru HCLK_VDPU_ROOT>,
						 <&cru ACLK_VDPU_ROOT>;
					pm_qos = <&qos_rkvdec1>;
					#power-domain-cells = <0>;
				};
				power-domain@RK3588_PD_RGA30 {
					reg = <RK3588_PD_RGA30>;
					clocks = <&cru ACLK_RGA3_0>,
						 <&cru HCLK_RGA3_0>;
					pm_qos = <&qos_rga3_0>;
					#power-domain-cells = <0>;
				};
			};
			power-domain@RK3588_PD_VOP {
				reg = <RK3588_PD_VOP>;
				clocks = <&cru PCLK_VOP_ROOT>,
					 <&cru HCLK_VOP_ROOT>,
					 <&cru ACLK_VOP>;
				pm_qos = <&qos_vop_m0>,
					 <&qos_vop_m1>;
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <0>;

				power-domain@RK3588_PD_VO0 {
					reg = <RK3588_PD_VO0>;
					clocks = <&cru PCLK_VO0_ROOT>,
						 <&cru PCLK_VO0_S_ROOT>,
						 <&cru HCLK_VO0_S_ROOT>,
						 <&cru ACLK_VO0_ROOT>,
						 <&cru HCLK_HDCP0>,
						 <&cru ACLK_HDCP0>,
						 <&cru HCLK_VOP_ROOT>;
					pm_qos = <&qos_hdcp0>;
					#power-domain-cells = <0>;
				};
			};
			power-domain@RK3588_PD_VO1 {
				reg = <RK3588_PD_VO1>;
				clocks = <&cru PCLK_VO1_ROOT>,
					 <&cru PCLK_VO1_S_ROOT>,
					 <&cru HCLK_VO1_S_ROOT>,
					 <&cru HCLK_HDCP1>,
					 <&cru ACLK_HDCP1>,
					 <&cru ACLK_HDMIRX_ROOT>,
					 <&cru HCLK_VO1USB_TOP_ROOT>;
				pm_qos = <&qos_hdcp1>,
					 <&qos_hdmirx>;
				#power-domain-cells = <0>;
			};
			power-domain@RK3588_PD_VI {
				reg = <RK3588_PD_VI>;
				clocks = <&cru HCLK_VI_ROOT>,
					 <&cru PCLK_VI_ROOT>,
					 <&cru HCLK_ISP0>,
					 <&cru ACLK_ISP0>,
					 <&cru HCLK_VICAP>,
					 <&cru ACLK_VICAP>;
				pm_qos = <&qos_isp0_mro>,
					 <&qos_isp0_mwo>,
					 <&qos_vicap_m0>,
					 <&qos_vicap_m1>;
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <0>;

				power-domain@RK3588_PD_ISP1 {
					reg = <RK3588_PD_ISP1>;
					clocks = <&cru HCLK_ISP1>,
						 <&cru ACLK_ISP1>,
						 <&cru HCLK_VI_ROOT>,
						 <&cru PCLK_VI_ROOT>;
					pm_qos = <&qos_isp1_mwo>,
						 <&qos_isp1_mro>;
					#power-domain-cells = <0>;
				};
				power-domain@RK3588_PD_FEC {
					reg = <RK3588_PD_FEC>;
					clocks = <&cru HCLK_FISHEYE0>,
						 <&cru ACLK_FISHEYE0>,
						 <&cru HCLK_FISHEYE1>,
						 <&cru ACLK_FISHEYE1>,
						 <&cru PCLK_VI_ROOT>;
					pm_qos = <&qos_fisheye0>,
						 <&qos_fisheye1>;
					#power-domain-cells = <0>;
				};
			};
			power-domain@RK3588_PD_RGA31 {
				reg = <RK3588_PD_RGA31>;
				clocks = <&cru HCLK_RGA3_1>,
					 <&cru ACLK_RGA3_1>;
				pm_qos = <&qos_rga3_1>;
				#power-domain-cells = <0>;
			};
			power-domain@RK3588_PD_USB {
				reg = <RK3588_PD_USB>;
				clocks = <&cru PCLK_PHP_ROOT>,
					 <&cru ACLK_USB_ROOT>,
					 <&cru ACLK_USB>,
					 <&cru HCLK_USB_ROOT>,
					 <&cru HCLK_HOST0>,
					 <&cru HCLK_HOST_ARB0>,
					 <&cru HCLK_HOST1>,
					 <&cru HCLK_HOST_ARB1>;
				pm_qos = <&qos_usb3_0>,
					 <&qos_usb3_1>,
					 <&qos_usb2host_0>,
					 <&qos_usb2host_1>;
				#power-domain-cells = <0>;
			};
			power-domain@RK3588_PD_GMAC {
				reg = <RK3588_PD_GMAC>;
				clocks = <&cru PCLK_PHP_ROOT>,
					 <&cru ACLK_PCIE_ROOT>,
					 <&cru ACLK_PHP_ROOT>;
				#power-domain-cells = <0>;
			};
			power-domain@RK3588_PD_PCIE {
				reg = <RK3588_PD_PCIE>;
				clocks = <&cru PCLK_PHP_ROOT>,
					 <&cru ACLK_PCIE_ROOT>,
					 <&cru ACLK_PHP_ROOT>;
				#power-domain-cells = <0>;
			};
			power-domain@RK3588_PD_SDIO {
				reg = <RK3588_PD_SDIO>;
				clocks = <&cru HCLK_SDIO>,
					 <&cru HCLK_NVM_ROOT>;
				pm_qos = <&qos_sdio>;
				#power-domain-cells = <0>;
			};
			power-domain@RK3588_PD_AUDIO {
				reg = <RK3588_PD_AUDIO>;
				clocks = <&cru HCLK_AUDIO_ROOT>,
					 <&cru PCLK_AUDIO_ROOT>;
				#power-domain-cells = <0>;
			};
			power-domain@RK3588_PD_SDMMC {
				reg = <RK3588_PD_SDMMC>;
				pm_qos = <&qos_sdmmc>;
				#power-domain-cells = <0>;
			};
		};
	};

	av1d: video-codec@fdc70000 {
		compatible = "rockchip,rk3588-av1-vpu";
		reg = <0x0 0xfdc70000 0x0 0x800>;
		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "vdpu";
		assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
		assigned-clock-rates = <400000000>, <400000000>;
		clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
		clock-names = "aclk", "hclk";
		power-domains = <&power RK3588_PD_AV1>;
		resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
	};

	vop: vop@fdd90000 {
		compatible = "rockchip,rk3588-vop";
		reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
		reg-names = "vop", "gamma-lut";
		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru ACLK_VOP>,
			 <&cru HCLK_VOP>,
			 <&cru DCLK_VOP0>,
			 <&cru DCLK_VOP1>,
			 <&cru DCLK_VOP2>,
			 <&cru DCLK_VOP3>,
			 <&cru PCLK_VOP_ROOT>;
		clock-names = "aclk",
			      "hclk",
			      "dclk_vp0",
			      "dclk_vp1",
			      "dclk_vp2",
			      "dclk_vp3",
			      "pclk_vop";
		iommus = <&vop_mmu>;
		power-domains = <&power RK3588_PD_VOP>;
		rockchip,grf = <&sys_grf>;
		rockchip,vop-grf = <&vop_grf>;
		rockchip,vo1-grf = <&vo1_grf>;
		rockchip,pmu = <&pmu>;
		status = "disabled";

		vop_out: ports {
			#address-cells = <1>;
			#size-cells = <0>;

			vp0: port@0 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;
			};

			vp1: port@1 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <1>;
			};

			vp2: port@2 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <2>;
			};

			vp3: port@3 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <3>;
			};
		};
	};

	vop_mmu: iommu@fdd97e00 {
		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
		reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
		clock-names = "aclk", "iface";
		#iommu-cells = <0>;
		power-domains = <&power RK3588_PD_VOP>;
		status = "disabled";
	};

	i2s4_8ch: i2s@fddc0000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x0 0xfddc0000 0x0 0x1000>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
		assigned-clock-parents = <&cru PLL_AUPLL>;
		dmas = <&dmac2 0>;
		dma-names = "tx";
		power-domains = <&power RK3588_PD_VO0>;
		resets = <&cru SRST_M_I2S4_8CH_TX>;
		reset-names = "tx-m";
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s5_8ch: i2s@fddf0000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x0 0xfddf0000 0x0 0x1000>;
		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
		assigned-clock-parents = <&cru PLL_AUPLL>;
		dmas = <&dmac2 2>;
		dma-names = "tx";
		power-domains = <&power RK3588_PD_VO1>;
		resets = <&cru SRST_M_I2S5_8CH_TX>;
		reset-names = "tx-m";
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s9_8ch: i2s@fddfc000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x0 0xfddfc000 0x0 0x1000>;
		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
		assigned-clock-parents = <&cru PLL_AUPLL>;
		dmas = <&dmac2 23>;
		dma-names = "rx";
		power-domains = <&power RK3588_PD_VO1>;
		resets = <&cru SRST_M_I2S9_8CH_RX>;
		reset-names = "rx-m";
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	qos_gpu_m0: qos@fdf35000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf35000 0x0 0x20>;
	};

	qos_gpu_m1: qos@fdf35200 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf35200 0x0 0x20>;
	};

	qos_gpu_m2: qos@fdf35400 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf35400 0x0 0x20>;
	};

	qos_gpu_m3: qos@fdf35600 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf35600 0x0 0x20>;
	};

	qos_rga3_1: qos@fdf36000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf36000 0x0 0x20>;
	};

	qos_sdio: qos@fdf39000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf39000 0x0 0x20>;
	};

	qos_sdmmc: qos@fdf3d800 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf3d800 0x0 0x20>;
	};

	qos_usb3_1: qos@fdf3e000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf3e000 0x0 0x20>;
	};

	qos_usb3_0: qos@fdf3e200 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf3e200 0x0 0x20>;
	};

	qos_usb2host_0: qos@fdf3e400 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf3e400 0x0 0x20>;
	};

	qos_usb2host_1: qos@fdf3e600 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf3e600 0x0 0x20>;
	};

	qos_fisheye0: qos@fdf40000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf40000 0x0 0x20>;
	};

	qos_fisheye1: qos@fdf40200 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf40200 0x0 0x20>;
	};

	qos_isp0_mro: qos@fdf40400 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf40400 0x0 0x20>;
	};

	qos_isp0_mwo: qos@fdf40500 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf40500 0x0 0x20>;
	};

	qos_vicap_m0: qos@fdf40600 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf40600 0x0 0x20>;
	};

	qos_vicap_m1: qos@fdf40800 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf40800 0x0 0x20>;
	};

	qos_isp1_mwo: qos@fdf41000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf41000 0x0 0x20>;
	};

	qos_isp1_mro: qos@fdf41100 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf41100 0x0 0x20>;
	};

	qos_rkvenc0_m0ro: qos@fdf60000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf60000 0x0 0x20>;
	};

	qos_rkvenc0_m1ro: qos@fdf60200 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf60200 0x0 0x20>;
	};

	qos_rkvenc0_m2wo: qos@fdf60400 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf60400 0x0 0x20>;
	};

	qos_rkvenc1_m0ro: qos@fdf61000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf61000 0x0 0x20>;
	};

	qos_rkvenc1_m1ro: qos@fdf61200 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf61200 0x0 0x20>;
	};

	qos_rkvenc1_m2wo: qos@fdf61400 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf61400 0x0 0x20>;
	};

	qos_rkvdec0: qos@fdf62000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf62000 0x0 0x20>;
	};

	qos_rkvdec1: qos@fdf63000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf63000 0x0 0x20>;
	};

	qos_av1: qos@fdf64000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf64000 0x0 0x20>;
	};

	qos_iep: qos@fdf66000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf66000 0x0 0x20>;
	};

	qos_jpeg_dec: qos@fdf66200 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf66200 0x0 0x20>;
	};

	qos_jpeg_enc0: qos@fdf66400 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf66400 0x0 0x20>;
	};

	qos_jpeg_enc1: qos@fdf66600 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf66600 0x0 0x20>;
	};

	qos_jpeg_enc2: qos@fdf66800 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf66800 0x0 0x20>;
	};

	qos_jpeg_enc3: qos@fdf66a00 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf66a00 0x0 0x20>;
	};

	qos_rga2_mro: qos@fdf66c00 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf66c00 0x0 0x20>;
	};

	qos_rga2_mwo: qos@fdf66e00 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf66e00 0x0 0x20>;
	};

	qos_rga3_0: qos@fdf67000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf67000 0x0 0x20>;
	};

	qos_vdpu: qos@fdf67200 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf67200 0x0 0x20>;
	};

	qos_npu1: qos@fdf70000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf70000 0x0 0x20>;
	};

	qos_npu2: qos@fdf71000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf71000 0x0 0x20>;
	};

	qos_npu0_mwr: qos@fdf72000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf72000 0x0 0x20>;
	};

	qos_npu0_mro: qos@fdf72200 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf72200 0x0 0x20>;
	};

	qos_mcu_npu: qos@fdf72400 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf72400 0x0 0x20>;
	};

	qos_hdcp0: qos@fdf80000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf80000 0x0 0x20>;
	};

	qos_hdcp1: qos@fdf81000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf81000 0x0 0x20>;
	};

	qos_hdmirx: qos@fdf81200 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf81200 0x0 0x20>;
	};

	qos_vop_m0: qos@fdf82000 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf82000 0x0 0x20>;
	};

	qos_vop_m1: qos@fdf82200 {
		compatible = "rockchip,rk3588-qos", "syscon";
		reg = <0x0 0xfdf82200 0x0 0x20>;
	};

	dfi: dfi@fe060000 {
		reg = <0x00 0xfe060000 0x00 0x10000>;
		compatible = "rockchip,rk3588-dfi";
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
		rockchip,pmu = <&pmu1grf>;
	};

	pcie2x1l1: pcie@fe180000 {
		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
		bus-range = <0x30 0x3f>;
		clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
			 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
			 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
		clock-names = "aclk_mst", "aclk_slv",
			      "aclk_dbi", "pclk",
			      "aux", "pipe";
		device_type = "pci";
		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
				<0 0 0 2 &pcie2x1l1_intc 1>,
				<0 0 0 3 &pcie2x1l1_intc 2>,
				<0 0 0 4 &pcie2x1l1_intc 3>;
		linux,pci-domain = <3>;
		max-link-speed = <2>;
		msi-map = <0x3000 &its0 0x3000 0x1000>;
		num-lanes = <1>;
		phys = <&combphy2_psu PHY_TYPE_PCIE>;
		phy-names = "pcie-phy";
		power-domains = <&power RK3588_PD_PCIE>;
		ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
			 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
			 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
		reg = <0xa 0x40c00000 0x0 0x00400000>,
		      <0x0 0xfe180000 0x0 0x00010000>,
		      <0x0 0xf3000000 0x0 0x00100000>;
		reg-names = "dbi", "apb", "config";
		resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
		reset-names = "pwr", "pipe";
		#address-cells = <3>;
		#size-cells = <2>;
		status = "disabled";

		pcie2x1l1_intc: legacy-interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
		};
	};

	pcie2x1l2: pcie@fe190000 {
		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
		bus-range = <0x40 0x4f>;
		clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
			 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
			 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
		clock-names = "aclk_mst", "aclk_slv",
			      "aclk_dbi", "pclk",
			      "aux", "pipe";
		device_type = "pci";
		interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
				<0 0 0 2 &pcie2x1l2_intc 1>,
				<0 0 0 3 &pcie2x1l2_intc 2>,
				<0 0 0 4 &pcie2x1l2_intc 3>;
		linux,pci-domain = <4>;
		max-link-speed = <2>;
		msi-map = <0x4000 &its0 0x4000 0x1000>;
		num-lanes = <1>;
		phys = <&combphy0_ps PHY_TYPE_PCIE>;
		phy-names = "pcie-phy";
		power-domains = <&power RK3588_PD_PCIE>;
		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
			 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
		reg = <0xa 0x41000000 0x0 0x00400000>,
		      <0x0 0xfe190000 0x0 0x00010000>,
		      <0x0 0xf4000000 0x0 0x00100000>;
		reg-names = "dbi", "apb", "config";
		resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
		reset-names = "pwr", "pipe";
		#address-cells = <3>;
		#size-cells = <2>;
		status = "disabled";

		pcie2x1l2_intc: legacy-interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
		};
	};

	gmac1: ethernet@fe1c0000 {
		compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
		reg = <0x0 0xfe1c0000 0x0 0x10000>;
		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "macirq", "eth_wake_irq";
		clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
			 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
			 <&cru CLK_GMAC1_PTP_REF>;
		clock-names = "stmmaceth", "clk_mac_ref",
			      "pclk_mac", "aclk_mac",
			      "ptp_ref";
		power-domains = <&power RK3588_PD_GMAC>;
		resets = <&cru SRST_A_GMAC1>;
		reset-names = "stmmaceth";
		rockchip,grf = <&sys_grf>;
		rockchip,php-grf = <&php_grf>;
		snps,axi-config = <&gmac1_stmmac_axi_setup>;
		snps,mixed-burst;
		snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
		snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
		snps,tso;
		status = "disabled";

		mdio1: mdio {
			compatible = "snps,dwmac-mdio";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		gmac1_stmmac_axi_setup: stmmac-axi-config {
			snps,blen = <0 0 0 0 16 8 4>;
			snps,wr_osr_lmt = <4>;
			snps,rd_osr_lmt = <8>;
		};

		gmac1_mtl_rx_setup: rx-queues-config {
			snps,rx-queues-to-use = <2>;
			queue0 {};
			queue1 {};
		};

		gmac1_mtl_tx_setup: tx-queues-config {
			snps,tx-queues-to-use = <2>;
			queue0 {};
			queue1 {};
		};
	};

	sata0: sata@fe210000 {
		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
		reg = <0 0xfe210000 0 0x1000>;
		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
			 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
			 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
		clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
		ports-implemented = <0x1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		sata-port@0 {
			reg = <0>;
			hba-port-cap = <HBA_PORT_FBSCP>;
			phys = <&combphy0_ps PHY_TYPE_SATA>;
			phy-names = "sata-phy";
			snps,rx-ts-max = <32>;
			snps,tx-ts-max = <32>;
		};
	};

	sata2: sata@fe230000 {
		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
		reg = <0 0xfe230000 0 0x1000>;
		interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
			 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
			 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
		clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
		ports-implemented = <0x1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		sata-port@0 {
			reg = <0>;
			hba-port-cap = <HBA_PORT_FBSCP>;
			phys = <&combphy2_psu PHY_TYPE_SATA>;
			phy-names = "sata-phy";
			snps,rx-ts-max = <32>;
			snps,tx-ts-max = <32>;
		};
	};

	sfc: spi@fe2b0000 {
		compatible = "rockchip,sfc";
		reg = <0x0 0xfe2b0000 0x0 0x4000>;
		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
		clock-names = "clk_sfc", "hclk_sfc";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	sdmmc: mmc@fe2c0000 {
		compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xfe2c0000 0x0 0x4000>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		max-frequency = <200000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
		power-domains = <&power RK3588_PD_SDMMC>;
		status = "disabled";
	};

	sdio: mmc@fe2d0000 {
		compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x00 0xfe2d0000 0x00 0x4000>;
		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		max-frequency = <200000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdiom1_pins>;
		power-domains = <&power RK3588_PD_SDIO>;
		status = "disabled";
	};

	sdhci: mmc@fe2e0000 {
		compatible = "rockchip,rk3588-dwcmshc";
		reg = <0x0 0xfe2e0000 0x0 0x10000>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
		assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
		assigned-clock-rates = <200000000>, <24000000>, <200000000>;
		clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
			 <&cru TMCLK_EMMC>;
		clock-names = "core", "bus", "axi", "block", "timer";
		max-frequency = <200000000>;
		pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
			    <&emmc_cmd>, <&emmc_data_strobe>;
		pinctrl-names = "default";
		resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
			 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
			 <&cru SRST_T_EMMC>;
		reset-names = "core", "bus", "axi", "block", "timer";
		status = "disabled";
	};

	i2s0_8ch: i2s@fe470000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x0 0xfe470000 0x0 0x1000>;
		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
		assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
		dmas = <&dmac0 0>, <&dmac0 1>;
		dma-names = "tx", "rx";
		power-domains = <&power RK3588_PD_AUDIO>;
		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
		reset-names = "tx-m", "rx-m";
		rockchip,trcm-sync-tx-only;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_lrck
			     &i2s0_sclk
			     &i2s0_sdi0
			     &i2s0_sdi1
			     &i2s0_sdi2
			     &i2s0_sdi3
			     &i2s0_sdo0
			     &i2s0_sdo1
			     &i2s0_sdo2
			     &i2s0_sdo3>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s1_8ch: i2s@fe480000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x0 0xfe480000 0x0 0x1000>;
		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		dmas = <&dmac0 2>, <&dmac0 3>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
		reset-names = "tx-m", "rx-m";
		rockchip,trcm-sync-tx-only;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1m0_lrck
			     &i2s1m0_sclk
			     &i2s1m0_sdi0
			     &i2s1m0_sdi1
			     &i2s1m0_sdi2
			     &i2s1m0_sdi3
			     &i2s1m0_sdo0
			     &i2s1m0_sdo1
			     &i2s1m0_sdo2
			     &i2s1m0_sdo3>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s2_2ch: i2s@fe490000 {
		compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
		reg = <0x0 0xfe490000 0x0 0x1000>;
		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
		clock-names = "i2s_clk", "i2s_hclk";
		assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
		assigned-clock-parents = <&cru PLL_AUPLL>;
		dmas = <&dmac1 0>, <&dmac1 1>;
		dma-names = "tx", "rx";
		power-domains = <&power RK3588_PD_AUDIO>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s2m1_lrck
			     &i2s2m1_sclk
			     &i2s2m1_sdi
			     &i2s2m1_sdo>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s3_2ch: i2s@fe4a0000 {
		compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
		reg = <0x0 0xfe4a0000 0x0 0x1000>;
		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
		clock-names = "i2s_clk", "i2s_hclk";
		assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
		assigned-clock-parents = <&cru PLL_AUPLL>;
		dmas = <&dmac1 2>, <&dmac1 3>;
		dma-names = "tx", "rx";
		power-domains = <&power RK3588_PD_AUDIO>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s3_lrck
			     &i2s3_sclk
			     &i2s3_sdi
			     &i2s3_sdo>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	gic: interrupt-controller@fe600000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
		      <0x0 0xfe680000 0 0x100000>; /* GICR */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-controller;
		mbi-alias = <0x0 0xfe610000>;
		mbi-ranges = <424 56>;
		msi-controller;
		ranges;
		#address-cells = <2>;
		#interrupt-cells = <4>;
		#size-cells = <2>;

		its0: msi-controller@fe640000 {
			compatible = "arm,gic-v3-its";
			reg = <0x0 0xfe640000 0x0 0x20000>;
			msi-controller;
			#msi-cells = <1>;
		};

		its1: msi-controller@fe660000 {
			compatible = "arm,gic-v3-its";
			reg = <0x0 0xfe660000 0x0 0x20000>;
			msi-controller;
			#msi-cells = <1>;
		};

		ppi-partitions {
			ppi_partition0: interrupt-partition-0 {
				affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
			};

			ppi_partition1: interrupt-partition-1 {
				affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
			};
		};
	};

	dmac0: dma-controller@fea10000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0xfea10000 0x0 0x4000>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
		arm,pl330-periph-burst;
		clocks = <&cru ACLK_DMAC0>;
		clock-names = "apb_pclk";
		#dma-cells = <1>;
	};

	dmac1: dma-controller@fea30000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0xfea30000 0x0 0x4000>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
		arm,pl330-periph-burst;
		clocks = <&cru ACLK_DMAC1>;
		clock-names = "apb_pclk";
		#dma-cells = <1>;
	};

	i2c1: i2c@fea90000 {
		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
		reg = <0x0 0xfea90000 0x0 0x1000>;
		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-0 = <&i2c1m0_xfer>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@feaa0000 {
		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
		reg = <0x0 0xfeaa0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-0 = <&i2c2m0_xfer>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c3: i2c@feab0000 {
		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
		reg = <0x0 0xfeab0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-0 = <&i2c3m0_xfer>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c4: i2c@feac0000 {
		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
		reg = <0x0 0xfeac0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-0 = <&i2c4m0_xfer>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c5: i2c@fead0000 {
		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
		reg = <0x0 0xfead0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-0 = <&i2c5m0_xfer>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	timer0: timer@feae0000 {
		compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
		reg = <0x0 0xfeae0000 0x0 0x20>;
		interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
		clock-names = "pclk", "timer";
	};

	wdt: watchdog@feaf0000 {
		compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
		reg = <0x0 0xfeaf0000 0x0 0x100>;
		clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
		clock-names = "tclk", "pclk";
		interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	spi0: spi@feb00000 {
		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfeb00000 0x0 0x1000>;
		interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 14>, <&dmac0 15>;
		dma-names = "tx", "rx";
		num-cs = <2>;
		pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi1: spi@feb10000 {
		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfeb10000 0x0 0x1000>;
		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 16>, <&dmac0 17>;
		dma-names = "tx", "rx";
		num-cs = <2>;
		pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi2: spi@feb20000 {
		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfeb20000 0x0 0x1000>;
		interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac1 15>, <&dmac1 16>;
		dma-names = "tx", "rx";
		num-cs = <2>;
		pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi3: spi@feb30000 {
		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfeb30000 0x0 0x1000>;
		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac1 17>, <&dmac1 18>;
		dma-names = "tx", "rx";
		num-cs = <2>;
		pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	uart1: serial@feb40000 {
		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfeb40000 0x0 0x100>;
		interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac0 8>, <&dmac0 9>;
		dma-names = "tx", "rx";
		pinctrl-0 = <&uart1m1_xfer>;
		pinctrl-names = "default";
		reg-io-width = <4>;
		reg-shift = <2>;
		status = "disabled";
	};

	uart2: serial@feb50000 {
		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfeb50000 0x0 0x100>;
		interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac0 10>, <&dmac0 11>;
		dma-names = "tx", "rx";
		pinctrl-0 = <&uart2m1_xfer>;
		pinctrl-names = "default";
		reg-io-width = <4>;
		reg-shift = <2>;
		status = "disabled";
	};

	uart3: serial@feb60000 {
		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfeb60000 0x0 0x100>;
		interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac0 12>, <&dmac0 13>;
		dma-names = "tx", "rx";
		pinctrl-0 = <&uart3m1_xfer>;
		pinctrl-names = "default";
		reg-io-width = <4>;
		reg-shift = <2>;
		status = "disabled";
	};

	uart4: serial@feb70000 {
		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfeb70000 0x0 0x100>;
		interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac1 9>, <&dmac1 10>;
		dma-names = "tx", "rx";
		pinctrl-0 = <&uart4m1_xfer>;
		pinctrl-names = "default";
		reg-io-width = <4>;
		reg-shift = <2>;
		status = "disabled";
	};

	uart5: serial@feb80000 {
		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfeb80000 0x0 0x100>;
		interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac1 11>, <&dmac1 12>;
		dma-names = "tx", "rx";
		pinctrl-0 = <&uart5m1_xfer>;
		pinctrl-names = "default";
		reg-io-width = <4>;
		reg-shift = <2>;
		status = "disabled";
	};

	uart6: serial@feb90000 {
		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfeb90000 0x0 0x100>;
		interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac1 13>, <&dmac1 14>;
		dma-names = "tx", "rx";
		pinctrl-0 = <&uart6m1_xfer>;
		pinctrl-names = "default";
		reg-io-width = <4>;
		reg-shift = <2>;
		status = "disabled";
	};

	uart7: serial@feba0000 {
		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfeba0000 0x0 0x100>;
		interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac2 7>, <&dmac2 8>;
		dma-names = "tx", "rx";
		pinctrl-0 = <&uart7m1_xfer>;
		pinctrl-names = "default";
		reg-io-width = <4>;
		reg-shift = <2>;
		status = "disabled";
	};

	uart8: serial@febb0000 {
		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfebb0000 0x0 0x100>;
		interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac2 9>, <&dmac2 10>;
		dma-names = "tx", "rx";
		pinctrl-0 = <&uart8m1_xfer>;
		pinctrl-names = "default";
		reg-io-width = <4>;
		reg-shift = <2>;
		status = "disabled";
	};

	uart9: serial@febc0000 {
		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfebc0000 0x0 0x100>;
		interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac2 11>, <&dmac2 12>;
		dma-names = "tx", "rx";
		pinctrl-0 = <&uart9m1_xfer>;
		pinctrl-names = "default";
		reg-io-width = <4>;
		reg-shift = <2>;
		status = "disabled";
	};

	pwm4: pwm@febd0000 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebd0000 0x0 0x10>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm4m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm5: pwm@febd0010 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebd0010 0x0 0x10>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm5m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm6: pwm@febd0020 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebd0020 0x0 0x10>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm6m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm7: pwm@febd0030 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebd0030 0x0 0x10>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm7m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm8: pwm@febe0000 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebe0000 0x0 0x10>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm8m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm9: pwm@febe0010 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebe0010 0x0 0x10>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm9m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm10: pwm@febe0020 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebe0020 0x0 0x10>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm10m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm11: pwm@febe0030 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebe0030 0x0 0x10>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm11m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm12: pwm@febf0000 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebf0000 0x0 0x10>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm12m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm13: pwm@febf0010 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebf0010 0x0 0x10>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm13m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm14: pwm@febf0020 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebf0020 0x0 0x10>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm14m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm15: pwm@febf0030 {
		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfebf0030 0x0 0x10>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		pinctrl-0 = <&pwm15m0_pins>;
		pinctrl-names = "default";
		#pwm-cells = <3>;
		status = "disabled";
	};

	thermal_zones: thermal-zones {
		/* sensor near the center of the SoC */
		package_thermal: package-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsadc 0>;

			trips {
				package_crit: package-crit {
					temperature = <115000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};

		/* sensor between A76 cores 0 and 1 */
		bigcore0_thermal: bigcore0-thermal {
			polling-delay-passive = <100>;
			polling-delay = <0>;
			thermal-sensors = <&tsadc 1>;

			trips {
				bigcore0_alert: bigcore0-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				bigcore0_crit: bigcore0-crit {
					temperature = <115000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&bigcore0_alert>;
					cooling-device =
						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		/* sensor between A76 cores 2 and 3 */
		bigcore2_thermal: bigcore2-thermal {
			polling-delay-passive = <100>;
			polling-delay = <0>;
			thermal-sensors = <&tsadc 2>;

			trips {
				bigcore2_alert: bigcore2-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				bigcore2_crit: bigcore2-crit {
					temperature = <115000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&bigcore2_alert>;
					cooling-device =
						<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		/* sensor between the four A55 cores */
		little_core_thermal: littlecore-thermal {
			polling-delay-passive = <100>;
			polling-delay = <0>;
			thermal-sensors = <&tsadc 3>;

			trips {
				littlecore_alert: littlecore-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				littlecore_crit: littlecore-crit {
					temperature = <115000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&littlecore_alert>;
					cooling-device =
						<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		/* sensor near the PD_CENTER power domain */
		center_thermal: center-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsadc 4>;

			trips {
				center_crit: center-crit {
					temperature = <115000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};

		gpu_thermal: gpu-thermal {
			polling-delay-passive = <100>;
			polling-delay = <0>;
			thermal-sensors = <&tsadc 5>;

			trips {
				gpu_alert: gpu-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				gpu_crit: gpu-crit {
					temperature = <115000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&gpu_alert>;
					cooling-device =
						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		npu_thermal: npu-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsadc 6>;

			trips {
				npu_crit: npu-crit {
					temperature = <115000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
	};

	tsadc: tsadc@fec00000 {
		compatible = "rockchip,rk3588-tsadc";
		reg = <0x0 0xfec00000 0x0 0x400>;
		interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
		clock-names = "tsadc", "apb_pclk";
		assigned-clocks = <&cru CLK_TSADC>;
		assigned-clock-rates = <2000000>;
		resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
		reset-names = "tsadc-apb", "tsadc";
		rockchip,hw-tshut-temp = <120000>;
		rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
		rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
		pinctrl-0 = <&tsadc_gpio_func>;
		pinctrl-1 = <&tsadc_shut>;
		pinctrl-names = "gpio", "otpout";
		#thermal-sensor-cells = <1>;
		status = "disabled";
	};

	saradc: adc@fec10000 {
		compatible = "rockchip,rk3588-saradc";
		reg = <0x0 0xfec10000 0x0 0x10000>;
		interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
		#io-channel-cells = <1>;
		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
		clock-names = "saradc", "apb_pclk";
		resets = <&cru SRST_P_SARADC>;
		reset-names = "saradc-apb";
		status = "disabled";
	};

	i2c6: i2c@fec80000 {
		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
		reg = <0x0 0xfec80000 0x0 0x1000>;
		clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-0 = <&i2c6m0_xfer>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c7: i2c@fec90000 {
		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
		reg = <0x0 0xfec90000 0x0 0x1000>;
		clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-0 = <&i2c7m0_xfer>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c8: i2c@feca0000 {
		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
		reg = <0x0 0xfeca0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-0 = <&i2c8m0_xfer>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi4: spi@fecb0000 {
		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfecb0000 0x0 0x1000>;
		interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac2 13>, <&dmac2 14>;
		dma-names = "tx", "rx";
		num-cs = <2>;
		pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	otp: efuse@fecc0000 {
		compatible = "rockchip,rk3588-otp";
		reg = <0x0 0xfecc0000 0x0 0x400>;
		clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
			 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
		clock-names = "otp", "apb_pclk", "phy", "arb";
		resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
			 <&cru SRST_OTPC_ARB>;
		reset-names = "otp", "apb", "arb";
		#address-cells = <1>;
		#size-cells = <1>;

		cpu_code: cpu-code@2 {
			reg = <0x02 0x2>;
		};

		otp_id: id@7 {
			reg = <0x07 0x10>;
		};

		cpub0_leakage: cpu-leakage@17 {
			reg = <0x17 0x1>;
		};

		cpub1_leakage: cpu-leakage@18 {
			reg = <0x18 0x1>;
		};

		cpul_leakage: cpu-leakage@19 {
			reg = <0x19 0x1>;
		};

		log_leakage: log-leakage@1a {
			reg = <0x1a 0x1>;
		};

		gpu_leakage: gpu-leakage@1b {
			reg = <0x1b 0x1>;
		};

		otp_cpu_version: cpu-version@1c {
			reg = <0x1c 0x1>;
			bits = <3 3>;
		};

		npu_leakage: npu-leakage@28 {
			reg = <0x28 0x1>;
		};

		codec_leakage: codec-leakage@29 {
			reg = <0x29 0x1>;
		};
	};

	dmac2: dma-controller@fed10000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0xfed10000 0x0 0x4000>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
		arm,pl330-periph-burst;
		clocks = <&cru ACLK_DMAC2>;
		clock-names = "apb_pclk";
		#dma-cells = <1>;
	};

	hdptxphy_hdmi0: phy@fed60000 {
		compatible = "rockchip,rk3588-hdptx-phy";
		reg = <0x0 0xfed60000 0x0 0x2000>;
		clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
		clock-names = "ref", "apb";
		#phy-cells = <0>;
		resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
			 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
			 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
			 <&cru SRST_HDPTX0_LCPLL>;
		reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
			      "lcpll";
		rockchip,grf = <&hdptxphy0_grf>;
		status = "disabled";
	};

	usbdp_phy0: phy@fed80000 {
		compatible = "rockchip,rk3588-usbdp-phy";
		reg = <0x0 0xfed80000 0x0 0x10000>;
		#phy-cells = <1>;
		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
			 <&cru CLK_USBDP_PHY0_IMMORTAL>,
			 <&cru PCLK_USBDPPHY0>,
			 <&u2phy0>;
		clock-names = "refclk", "immortal", "pclk", "utmi";
		resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
			 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
			 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
			 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
			 <&cru SRST_P_USBDPPHY0>;
		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
		rockchip,u2phy-grf = <&usb2phy0_grf>;
		rockchip,usb-grf = <&usb_grf>;
		rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
		rockchip,vo-grf = <&vo0_grf>;
		status = "disabled";
	};

	combphy0_ps: phy@fee00000 {
		compatible = "rockchip,rk3588-naneng-combphy";
		reg = <0x0 0xfee00000 0x0 0x100>;
		clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
			 <&cru PCLK_PHP_ROOT>;
		clock-names = "ref", "apb", "pipe";
		assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
		assigned-clock-rates = <100000000>;
		#phy-cells = <1>;
		resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
		reset-names = "phy", "apb";
		rockchip,pipe-grf = <&php_grf>;
		rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
		status = "disabled";
	};

	combphy2_psu: phy@fee20000 {
		compatible = "rockchip,rk3588-naneng-combphy";
		reg = <0x0 0xfee20000 0x0 0x100>;
		clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
			 <&cru PCLK_PHP_ROOT>;
		clock-names = "ref", "apb", "pipe";
		assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
		assigned-clock-rates = <100000000>;
		#phy-cells = <1>;
		resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
		reset-names = "phy", "apb";
		rockchip,pipe-grf = <&php_grf>;
		rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
		status = "disabled";
	};

	system_sram2: sram@ff001000 {
		compatible = "mmio-sram";
		reg = <0x0 0xff001000 0x0 0xef000>;
		ranges = <0x0 0x0 0xff001000 0xef000>;
		#address-cells = <1>;
		#size-cells = <1>;
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3588-pinctrl";
		ranges;
		rockchip,grf = <&ioc>;
		#address-cells = <2>;
		#size-cells = <2>;

		gpio0: gpio@fd8a0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfd8a0000 0x0 0x100>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
			gpio-controller;
			gpio-ranges = <&pinctrl 0 0 32>;
			interrupt-controller;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@fec20000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfec20000 0x0 0x100>;
			interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
			gpio-controller;
			gpio-ranges = <&pinctrl 0 32 32>;
			interrupt-controller;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@fec30000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfec30000 0x0 0x100>;
			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
			gpio-controller;
			gpio-ranges = <&pinctrl 0 64 32>;
			interrupt-controller;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@fec40000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfec40000 0x0 0x100>;
			interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
			gpio-controller;
			gpio-ranges = <&pinctrl 0 96 32>;
			interrupt-controller;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@fec50000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfec50000 0x0 0x100>;
			interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
			gpio-controller;
			gpio-ranges = <&pinctrl 0 128 32>;
			interrupt-controller;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
		};
	};
};

#include "rk3588-base-pinctrl.dtsi"