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path: root/drivers/pinctrl/sh-pfc/sh_pfc.h
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2020-09-15pinctrl: Rename sh-pfc to renesasGeert Uytterhoeven
The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
2020-07-14pinctrl: sh-pfc: pfc-r8a77951: Add R8A774E1 PFC supportLad Prabhakar
Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (R8A77951), however it doesn't have several automotive specific peripherals. Add automotive-specific pin groups/functions along with common pin groups/functions for supporting both r8a77951 and r8a774e1 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594138692-16816-13-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-05-15pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC supportLad Prabhakar
Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790), however it doesn't have several automotive specific peripherals. Add automotive-specific pin groups/functions along with common pin groups/functions for supporting both r8a7790 and r8a7742 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1588542414-14826-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-01-08pinctrl: sh-pfc: Split R-Car H3 support in two independent driversGeert Uytterhoeven
Despite using the same compatible values ("r8a7795"-based) because of historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+ (R8A77951) are really different SoCs, with different part numbers, and with different Pin Function Controller blocks. Reflect this in the pinctrl configuration, by replacing the existing CONFIG_PINCTRL_PFC_R8A7795 symbol by two new config symbols: CONFIG_PINCTRL_PFC_R8A77950 and CONFIG_PINCTRL_PFC_R8A77951. The latter are selected automatically, depending on the soon-to-be-introduced corresponding SoC-specific config options, and on the current common config option, to relax dependencies. Rename the individual pin control driver source files from pfc-r8a7795-es1.c to pfc-r8a77950.c, and from pfc-r8a7795.c to pfc-r8a77951.c, and make them truly independent. As both SoCs share the same compatible value, special care must be taken to match them to the correct pin control driver, if support for it is included in the running kernel. This will allow making support for early R-Car H3 revisions optional, the largest share of which is taken by the pin control driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191230083156.19191-1-geert+renesas@glider.be
2019-11-01pinctrl: sh-pfc: r8a7796: Add R8A77961 PFC supportGeert Uytterhoeven
Add support for the Pin Function Controller in the R-Car M3-W+ (R8A77961) SoC. R-Car M3-W+ is pin compatible with R-Car M3-W (R8A77960), which allows for both SoCs to share a driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023122955.12420-4-geert+renesas@glider.be
2019-11-01pinctrl: sh-pfc: Rename PINCTRL_PFC_R8A7796 to PINCTRL_PFC_R8A77960Geert Uytterhoeven
Rename CONFIG_PINCTRL_PFC_R8A7796 for R-Car M3-W (R8A77960) to CONFIG_PINCTRL_PFC_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_PINCTRL_PFC_R8A77961. Extend the dependency of CONFIG_PINCTRL_PFC_R8A77960 from CONFIG_ARCH_R8A7796 to CONFIG_ARCH_R8A77960, to relax dependencies for a future rename of the SoC configuration symbol. Rename r8a7796_pinmux_info to r8a77960_pinmux_info, as it contains an r8a77960-based name. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023122955.12420-3-geert+renesas@glider.be
2019-10-14pinctrl: sh-pfc: Fix PINMUX_IPSR_PHYS() to set GPSRKeiya Nobuta
This patch allows PINMUX_IPSR_PHYS() to set bits in GPSR. When assigning function to pin, GPSR should be set to peripheral function. For example when using SCL3, GPSR2 bit7 (PWM1_A pin) should be set to peripheral function. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060112.29819-1-nobuta.keiya@fujitsu.com Fixes: 50d1ba1764b3e00a ("pinctrl: sh-pfc: Add physical pin multiplexing helper macros") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-01pinctrl: sh-pfc: r8a77965: Add R8A774B1 PFC supportBiju Das
Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965), however it doesn't have several automotive specific peripherals. Add a r8a77965 specific pin groups/functions along with common pin groups/functions for supporting both r8a77965 and r8a774b1 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1568881036-4404-9-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-04pinctrl: sh-pfc: Remove obsolete SH_PFC_PIN_NAMED*() macrosGeert Uytterhoeven
Now all Renesas pin control drivers have been converted to use the new non-GPIO helper macros, SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG() are no longer used. Remove them. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: Add new non-GPIO helper macrosGeert Uytterhoeven
Add new macros for describing pins without GPIO functionality: - NOGP_ALL() expands to a list of PIN_id values, to be used for generating symbolic enum values, - PINMUX_NOGP_ALL() expands to a list of sh_pfc_pin entries, to list all pins and their capabilities. Both macros depend on an SoC-specific CPU_ALL_NOGP() macro, to be provided by each individual SoC pin control driver. The new macros offer two advantages over the existing SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG() macros: 1. They do not rely on PIN_NUMBER() macros and physical pin numbering, hence do not suffer from pin numbering confusion among different SoC/SiP packages. 2. They are similar in spirit to the existing scheme for handling pins with GPIO functionality. Note that internal to the driver, non-GPIO pins use a sequential numbering scheme which starts after the highest GPIO pin number in use. This value is calculated automatically, using two new helper macros, for systems with either 32-port bank (GP port style) or linear (PORT style) pin space. Sample expansion: GP_LAST = sizeof(union { char dummy[0] __attribute__((deprecated, deprecated)); char GP_0_0[(0 * 32) + 0] __attribute__((deprecated, deprecated)); char GP_0_1[(0 * 32) + 1] __attribute__((deprecated, deprecated)); ... char GP_7_3[(7 * 32) + 3] __attribute__((deprecated, deprecated)); }) Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-05-21pinctrl: sh-pfc: Add PORT_GP_27 helper macroGeert Uytterhoeven
This follows the style of the existing PORT_GP_X macros, and will be used by a follow-up patch for the r8a7778 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Move PIN_NONE to shared header fileGeert Uytterhoeven
Several drivers have identical definitions for PIN_NONE. Provide a definition with a SH_PFC_ prefix for general use in sh_pfc.h, and convert all drivers over to use it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthandGeert Uytterhoeven
It is very common for a pin to support both pull-up and pull-down functionality. Hence add a shorthand SH_PFC_PIN_CFG_PULL_UP_DOWN. This not only reduces typing, but also avoids the need for several line breaks, and makes many overly long lines shorter, improving readability. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variantGeert Uytterhoeven
There are two variants of the CPU_ALL_PORT() macro in use: 1. A three-parameter variant, to be provided for SoCs with a linear GPIO pin space ("PORT style"), 2. A two-parameter variant, to be provided for SoCs with 32-port GPIO banks ("GP port style"). Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and to increase naming consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentationGeert Uytterhoeven
- The IPSR field is meant for documentation only, - The function name refers to the pin function, not to the IPSR field. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-04-02pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fieldsGeert Uytterhoeven
Add a run-time check to the PINMUX_CFG_REG_VAR() macro, to ensure the number of provided enum IDs is correct. This cannot be done at build time, as the number of values depends on the variable-width fields in the config register. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fieldsGeert Uytterhoeven
Add build-time checks to the PINMUX_CFG_REG() and PINMUX_DATA_REG() macros, to ensure the number of provided enum IDs is correct. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macroGeert Uytterhoeven
Currently the PINMUX_DATA_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using the GROUP() macro. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macroGeert Uytterhoeven
Currently the PINMUX_CFG_REG_VAR() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence both the register field widths and the enum IDs are wrapped using the GROUP() macro. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macroGeert Uytterhoeven
Currently the PINMUX_CFG_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using a new macro GROUPS(). No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Introduce PINCTRL_SH_FUNC_GPIO helper symbolGeert Uytterhoeven
Pinctrl drivers for SuperH platforms use legacy function GPIOs. Currently this support is compiled in based on the SUPERH platform dependency, which hinders the introduction of compile-testing support for the affected pinctrl drivers. Introduce a new Kconfig symbol PINCTRL_SH_FUNC_GPIO, which is auto-selected when needed. This symbol in turn selects PINCTRL_SH_PFC_GPIO, to reduce the number of per-driver selects. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-11pinctrl: sh-pfc: Validate fixed-size field widths at build timeGeert Uytterhoeven
Add a build-time check, to ensure the register and field widths in descriptors for config registers with fixed-width fields are sane. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-lengthGeert Uytterhoeven
pinmux_cfg_reg.var_field_width[] is actually a variable-length array, terminated by a zero, and counting at most r_width entries. Usually the number of entries is much smaller than r_width, so the ability to catch bugs at compile time through an "excess elements in array initializer" warning is fairly limited. Hence make the array variable-length, decreasing kernel size slightly. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: Validate pins/marks in pin groups at build timeGeert Uytterhoeven
Add a build-time check, to ensure the number of pins and pin marks in a pin group matches. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-19pinctrl: sh-pfc: Add physical pin multiplexing helper macrosUlrich Hecht
Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: Add optional arg to VIN_DATA_PIN_GROUPJacopo Mondi
VIN data groups may appear on different sets of pins, usually named "vinX_data_[a|b]". The existing VIN_DATA_PIN_GROUP() does not support appending the '_a' or '_b' suffix, leading to the definition of group names not consistent with the ones defined using the SH_PFC_PIN_GROUP() macro. Fix this by making the VIN_DATA_PIN_GROUP macro a variadic one, which accepts an optional 'version' argument. Fixes: 423caa52534f ("pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to shared header file") Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06pinctrl: sh-pfc: Reduce kernel size for narrow VIN channelsGeert Uytterhoeven
Some VIN channels support less than 24 lanes. As union vin_data always consumes space for 24 lanes, this wastes memory. Hence introduce new smaller unions vin_data12 and vin_data16, to accommodate VIN channels with only 12 or 16 lanes. This reduces the static pin controller driver size by 320 bytes for R-Car V2H, and by 96 bytes for R-Car E2. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-09-19pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC supportFabrizio Castro
Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car E3 (a.k.a. r8a77990), however it doesn't have several automotive specific peripherals. Add a r8a77990 specific pin groups/functions along with common pin groups/functions for supporting both r8a77990 and r8a774c0 SoCs. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19pinctrl: sh-pfc: r8a7791: Add r8a7744 supportBiju Das
Renesas RZ/G1N (R8A7744) is pin compatible with R-Car M2-W/N (R8A7791/3) and RZ/G1M. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11pinctrl: sh-pfc: Convert to SPDX identifiersKuninori Morimoto
This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-28pinctrl: sh-pfc: r8a7796: Add R8A774A1 PFC supportBiju Das
Renesas RZ/G2M (r8a774a1) is pin compatible with R-Car M3-W (r8a7796), however it doesn't have several automotive specific peripherals. Add an r8a7796 specific pin groups/functions along with common pin groups/functions for supporting both r8a7796 and r8a774a1 SoCs. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-05-23pinctrl: sh-pfc: Initial R8A77990 PFC supportTakeshi Kihara
This patch adds initial pinctrl driver to support for the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-05-23pinctrl: sh-pfc: Add PORT_GP_11 helper macroTakeshi Kihara
This follows the style of existion PORT_GP_X macros and will be used by a follow-up patch for the r8a77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-05-16pinctrl: sh-pfc: Add r8a77470 PFC supportBiju Das
Add PFC support for the R8A77470 SoC including pin groups for some on-chip devices such as SCIF and MMC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-21pinctrl: sh-pfc: Add SH_PFC_PIN_GROUP_ALIAS()Geert Uytterhoeven
Add a macro to refer to another pin group with a different name. This will be used to rename wrongly-named pin groups, while retaining backwards compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-03-09pinctrl: sh-pfc: Add R8A77980 PFC supportSergei Shtylyov
Add the PFC support for the R8A77980 SoC including pin groups for some on-chip devices such as AVB, CAN-FD, GETHER, [H]SCIF, I2C, INTC-EX, MMC, MSIOF, PWM, and VIN... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-09pinctrl: sh-pfc: Add PORT_GP_CFG_25() helper macroSergei Shtylyov
They follow the style of the existing PORT_GP_CFG_<n>() macros and will be used by a follow-up patch for the R8A77980 SoC. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20pinctrl: sh-pfc: Initial R-Car M3-N supportJacopo Mondi
Add initial PFC support for R-Car M3-N (r8a77965) SoC. No groups or functions defined, just pin and registers enumeration. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-12-05pinctrl: sh-pfc: Add R8A77970 PFC supportSergei Shtylyov
Add the PFC support for the R8A77970 SoC including pin groups for some on-chip devices such as CAN-FD, [H]SCIF, I2C, INTC-EX, MMC, MSIOF, PWM, VIN... Based on the original (and large) patch by Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com>. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> [geert: Drop EtherAVB for now] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-11-28pinctrl: sh-pfc: Add PORT_GP_CFG_{6|22}() helper macrosSergei Shtylyov
They follow the style of the existing PORT_GP_CFG_<n>() macros and will be used by a follow-up patch for the R8A77970 SoC. Based on the original (and large) patch by Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com>. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: Save/restore registers for PSCI system suspendGeert Uytterhoeven
During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their pinctrl register state is lost. Note that as the boot loader skips most initialization after system resume, pinctrl register state differs from the state encountered during normal system boot, too. To fix this, save all GPIO and peripheral function select, module select, drive strength control, bias, and other I/O control registers during system suspend, and restore them during system resume. Note that to avoid overhead on platforms not needing it, the suspend/resume code has a build time dependency on sleep and PSCI support, and a runtime dependency on PSCI. Inspired by a patch in the BSP by Hien Dang. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: Add generic IOCTRL register descriptionGeert Uytterhoeven
Add a generic way to describe IOCTRL registers (for e.g. SD I/O voltage and time delay control), like is already done for config, drive, and bias registers. This makes the sh-pfc core code aware of these registers, which will ease introducing suspend/resume support later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: Remove obsolete sh_pfc_pin_to_bias_info()Geert Uytterhoeven
All users of sh_pfc_pin_to_bias_info() and the related data structures have been converted to sh_pfc_pin_to_bias_reg(), so those can be removed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2017-10-20pinctrl: sh-pfc: Add generic bias register descriptionGeert Uytterhoeven
Add a generic way to describe bias registers (for pull-up/down control), like is already done for config and drive registers. This makes the sh-pfc core code aware of these registers, which will ease introducing suspend/resume support later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2017-08-16pinctrl: sh-pfc: Initial R8A77995 PFC supportTakeshi Kihara
This patch adds initial pinctrl driver to support for the R8A77995 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: whitespace] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: Add PORT_GP_{10,2[01]} helper macrosYoshihiro Shimoda
This follows the style of existion PORT_GP_X macros and will be used by a follow-up patch for the r8a77995 SoC. Extracted from the initial r8a77995 patch in the BSP by Takeshi Kihara. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16pinctrl: sh-pfc: r8a7794: Add R8A7745 supportSergei Shtylyov
Renesas RZ/G1E (R8A7745) is pin compatible with R-Car E2 (R8A7794), however it doesn't have several automotive specific peripherals. Annotate all the items that only exist on the R-Car SoCs... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> [geert: Drop annotations, as they are implied by pin groups/functions] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16pinctrl: sh-pfc: r8a7791: Add R8A7743 supportSergei Shtylyov
Renesas RZ/G1M (R8A7743) is pin compatible with R-Car M2-W/N (R8A7791/3), however it doesn't have several automotive specific peripherals. Annotate all the items that only exist on the R-Car SoCs and only supply the pin groups/functions existing on a given SoC... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> [geert: Drop annotations, as they are implied by pin groups/functions] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-30pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0Geert Uytterhoeven
The Pin Function Controller module in the R-Car H3 ES2.0 differs from ES1.x in many ways. The goal is twofold: 1. Support both the ES1.x and ES2.0 SoC revisions in a single binary for now, 2. Make it clear which code supports ES1.x, so it can easily be identified and removed later, when production SoCs are deemed ubiquitous. Hence this patch: 1. Extracts the support for R-Car H3 ES1.x into a separate file, as the differences are quite large, 2. Adds code for detecting the SoC revision at runtime using the new soc_device_match() API, and selecting pinctrl tables for the actual SoC revision, 3. Replaces the core register and bitfield definitions by their counterparts for R-Car H3 ES2.0. The addition of pins, groups, and functions for the various on-chip devices is left to subsequent patches. The R-Car H3 ES2.0 register and bitfield definitions were extracted from a patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
2016-11-16pinctrl: sh-pfc: Support named pins with custom configurationNiklas Söderlund
Pins not associated with a GPIO port can still have other configuration parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named pins to be declared with a set of configurations. The new macro is an modification of SH_PFC_PIN_NAMED to allow for optional configuration to be assigned. The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be used to define pins not associated with a GPIO port. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>