| Age | Commit message (Expand) | Author |
|---|
| 2017-07-20 | arm64: atomics: Remove '&' from '+&' asm constraint in lse atomics | Will Deacon |
| 2017-05-09 | arm64: atomic_lse: match asm register sizes | Mark Rutland |
| 2016-09-09 | arm64: lse: convert lse alternatives NOP padding to use __nops | Will Deacon |
| 2016-06-16 | locking/atomic, arch/arm64: Implement atomic{,64}_fetch_{add,sub,and,andnot,o... | Will Deacon |
| 2016-06-16 | locking/atomic, arch/arm64: Generate LSE non-return cases using common macros | Will Deacon |
| 2016-02-26 | arm64: lse: deal with clobbered IP registers after branch via PLT | Ard Biesheuvel |
| 2015-11-05 | arm64: cmpxchg_dbl: fix return value type | Lorenzo Pieralisi |
| 2015-10-12 | arm64: atomics: implement native {relaxed, acquire, release} atomics | Will Deacon |
| 2015-07-29 | arm64: lse: fix lse cmpxchg code indentation | Will Deacon |
| 2015-07-27 | arm64: atomic64_dec_if_positive: fix incorrect branch condition | Will Deacon |
| 2015-07-27 | arm64: atomics: implement atomic{,64}_cmpxchg using cmpxchg | Will Deacon |
| 2015-07-27 | arm64: cmpxchg: avoid "cc" clobber in ll/sc routines | Will Deacon |
| 2015-07-27 | arm64: cmpxchg_dbl: patch in lse instructions when supported by the CPU | Will Deacon |
| 2015-07-27 | arm64: cmpxchg: patch in lse instructions when supported by the CPU | Will Deacon |
| 2015-07-27 | arm64: atomics: patch in lse instructions when supported by the CPU | Will Deacon |
| 2015-07-27 | arm64: introduce CONFIG_ARM64_LSE_ATOMICS as fallback to ll/sc atomics | Will Deacon |
