diff options
Diffstat (limited to 'drivers/i2c/busses/i2c-stm32f4.c')
| -rw-r--r-- | drivers/i2c/busses/i2c-stm32f4.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/i2c/busses/i2c-stm32f4.c b/drivers/i2c/busses/i2c-stm32f4.c index ba600d77a3f8..d6a69dfcac3f 100644 --- a/drivers/i2c/busses/i2c-stm32f4.c +++ b/drivers/i2c/busses/i2c-stm32f4.c @@ -232,10 +232,10 @@ static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev) * In standard mode: * t_scl_high = t_scl_low = CCR * I2C parent clk period * So to reach 100 kHz, we have: - * CCR = I2C parent rate / 100 kHz >> 1 + * CCR = I2C parent rate / (100 kHz * 2) * * For example with parent rate = 2 MHz: - * CCR = 2000000 / (100000 << 1) = 10 + * CCR = 2000000 / (100000 * 2) = 10 * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached * @@ -243,7 +243,7 @@ static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev) * parent rate is not higher than 46 MHz . As a result val * is at most 8 bits wide and so fits into the CCR bits [11:0]. */ - val = i2c_dev->parent_rate / (100000 << 1); + val = i2c_dev->parent_rate / (I2C_MAX_STANDARD_MODE_FREQ * 2); } else { /* * In fast mode, we compute CCR with duty = 0 as with low @@ -263,7 +263,7 @@ static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev) * parent rate is not higher than 46 MHz . As a result val * is at most 6 bits wide and so fits into the CCR bits [11:0]. */ - val = DIV_ROUND_UP(i2c_dev->parent_rate, 400000 * 3); + val = DIV_ROUND_UP(i2c_dev->parent_rate, I2C_MAX_FAST_MODE_FREQ * 3); /* Select Fast mode */ ccr |= STM32F4_I2C_CCR_FS; @@ -807,7 +807,7 @@ static int stm32f4_i2c_probe(struct platform_device *pdev) i2c_dev->speed = STM32_I2C_SPEED_STANDARD; ret = of_property_read_u32(np, "clock-frequency", &clk_rate); - if (!ret && clk_rate >= 400000) + if (!ret && clk_rate >= I2C_MAX_FAST_MODE_FREQ) i2c_dev->speed = STM32_I2C_SPEED_FAST; i2c_dev->dev = &pdev->dev; |