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author | David S. Miller <davem@davemloft.net> | 2021-06-29 10:46:23 -0700 |
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committer | David S. Miller <davem@davemloft.net> | 2021-06-29 10:46:23 -0700 |
commit | 7f4e5c5b8cb00138ad1a10cab87bbd1e2d4d3376 (patch) | |
tree | 4299fdf57fa2a7d1c6b649089736321a1f1d7cc8 /net/sctp/ipv6.c | |
parent | 84fe73996c2e7407006002ef92d7354a56b69fed (diff) | |
parent | 63c51453c82cddc27556233ff41041ea9fc49fe0 (diff) |
Merge branch 'dsa-rx-filtering'
Vladimir Oltean says:
====================
RX filtering in DSA
This is my fourth stab (identical to the third one except sent as
non-RFC) at creating a list of unicast and multicast addresses that the
DSA CPU ports must trap. I am reusing a lot of Tobias's work which he
submitted here:
https://patchwork.kernel.org/project/netdevbpf/cover/20210116012515.3152-1-tobias@waldekranz.com/
My additions to Tobias' work come in the form of taking some care that
additions and removals of host addresses are properly balanced, so that
we can do reference counting on them for cross-chip setups and multiple
bridges spanning the same switch (I am working on an NXP board where
both are real requirements).
During the last attempted submission of multiple CPU ports for DSA:
https://patchwork.kernel.org/project/netdevbpf/cover/20210410133454.4768-1-ansuelsmth@gmail.com/
it became clear that the concept of multiple CPU ports would not be
compatible with the idea of address learning on those CPU ports (when
those CPU ports are statically assigned to user ports, not in a LAG)
unless the switch supports complete FDB isolation, which most switches
do not. So DSA needs to manage in software all addresses that are
installed on the CPU port(s), which is what this patch set does.
Compared to all earlier attempts, this series does not fiddle with how
DSA operates the ports in standalone mode at all, just when bridged.
We need to sort that out properly, then any optimization that comes in
standalone mode (i.e. IFF_UNICAST_FLT) can come later.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
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