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authorTudor Ambarus <tudor.ambarus@microchip.com>2019-11-07 08:42:05 +0000
committerTudor Ambarus <tudor.ambarus@microchip.com>2019-11-11 08:56:39 +0200
commit7b678c69c0ca59ed4a1e65055b1e58918db38968 (patch)
tree08f9517771edcdd59046fffc155b272c3532eb75 /include
parentbb2dc7f46ad897ba1c2d8ae773c77601ba240932 (diff)
mtd: spi-nor: Merge spansion Quad Enable methods
Merge spansion_no_read_cr_quad_enable() spansion_read_cr_quad_enable() into spi_nor_sr2_bit1_quad_enable(). Reduce code duplication by introducing spi_nor_write_16bit_cr_and_check(). The Configuration Register contains bits that can be updated in future: FREEZE, CMP. Provide a generic method that allows updating all bits of the Configuration Register. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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