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| author | Arnd Bergmann <arnd@arndb.de> | 2024-09-05 10:13:40 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2024-09-05 10:13:44 +0000 |
| commit | 5d9e36498bea0e617c8bde1fca679f3a5e75007e (patch) | |
| tree | f711f844b8e7589c558ddeae459b565106b7f041 /include | |
| parent | 06b6879f0a07dd5c7a57b1ddaedbb0e4571d904b (diff) | |
| parent | cc41aa93bbafdfe4c4c9026d307adbb89c1d80fa (diff) | |
Merge tag 'renesas-dts-for-v6.12-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.12 (take two)
- Add support for Ethernet TSN and PCIe on the R-Car V4H SoC and the
White-Hawk (Single) development board,
- Add display support for the RZ/G2UL SoC and the RZ/G2UL SMARC EVk
board,
- Add I2C support for the RZ/G3S SoC and the RZ/G3S SMARC EVK board,
- Add support for HDMI audio on the RZ/G2L and RZ/G2LC SMARC EVK
boards,
- Add initial support for the RZ/V2H(P) (R9A09G057) SoC and the RZ/V2H
EVK board,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.12-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits)
arm64: dts: renesas: r8a779h0: Add family fallback for CSISP IP
arm64: dts: renesas: r8a779a0: Add family fallback for CSISP IP
arm64: dts: renesas: r8a779g0: Add family fallback for CSISP IP
arm64: dts: renesas: r8a779h0: Add family fallback for VIN IP
arm64: dts: renesas: r8a779a0: Add family fallback for VIN IP
arm64: dts: renesas: r8a779g0: Add family fallback for VIN IP
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable watchdog
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable OSTM, I2C, and SDHI
arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
arm64: dts: renesas: r9a09g057: Add SDHI0-SDHI2 nodes
arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodes
arm64: dts: renesas: r9a09g057: Add OSTM0-OSTM7 nodes
arm64: dts: renesas: Add initial DTS for RZ/V2H EVK board
arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoC
dt-bindings: soc: renesas: Document RZ/V2H EVK board
dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
arm64: dts: renesas: r9a07g043u11-smarc: Enable DU
arm64: dts: renesas: rzg2lc-smarc: Enable HDMI audio
arm64: dts: renesas: rzg2l-smarc: Enable HDMI audio
arm64: dts: renesas: r9a07g043u: Add DU node
...
Link: https://lore.kernel.org/r/cover.1725374275.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g057-cpg.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h new file mode 100644 index 000000000000..541e6d719bd6 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* Core Clock list */ +#define R9A09G057_SYS_0_PCLK 0 +#define R9A09G057_CA55_0_CORE_CLK0 1 +#define R9A09G057_CA55_0_CORE_CLK1 2 +#define R9A09G057_CA55_0_CORE_CLK2 3 +#define R9A09G057_CA55_0_CORE_CLK3 4 +#define R9A09G057_CA55_0_PERIPHCLK 5 +#define R9A09G057_CM33_CLK0 6 +#define R9A09G057_CST_0_SWCLKTCK 7 +#define R9A09G057_IOTOP_0_SHCLK 8 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */ |