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authorAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>2013-08-09 11:54:49 -0500
committerBorislav Petkov <bp@suse.de>2013-08-12 16:00:10 +0200
commit18b94f66f9537003cee30d475d79a57c58f1e1d8 (patch)
tree50250574b9e01bfd86b322635b7ef82a89f06538 /include/net/ip6_fib.h
parent7d64ac6422092adbbdaa279ab32f9d4c90a84558 (diff)
amd64_edac: Add ECC decoding support for newer F15h models
On newer models, support has been included for upto 4 DCT's, however, only DCT0 and DCT3 are currently configured (cf BKDG Section 2.10). Also, the routing DRAM Requests algorithm is different for F15h M30h. Thus it is cleaner to use a brand new function rather than adding quirks to the more generic f1x_match_to_this_node(). Refer to "2.10.5 DRAM Routing Requests" in the BKDG for further info. Tested on Fam15h M30h with ECC turned on using mce_amd_inj facility and verified to be functionally correct. While at it, verify if erratum workarounds for E505 and E637 still hold. From email conversations within AMD, the current status of the errata is: * Erratum 505: fixed in model 0x1, stepping 0x1 and later. * Erratum 637: not fixed. Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> [ Cleanups, corrections ] Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'include/net/ip6_fib.h')
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