diff options
| author | Wesley Sheng <wesley.sheng@microchip.com> | 2018-12-10 17:12:24 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2018-12-13 09:03:32 -0600 |
| commit | f7eb7b8a4f72b0d9dea69b09f58185ffab97fd35 (patch) | |
| tree | 44c8f6a837faf78d53bd2ad0308db0b3a5a2ea7f /include/linux/switchtec.h | |
| parent | 52d8db8e0cd7c28316514568fe5df0cfd4fa2075 (diff) | |
switchtec: Add MRPC DMA mode support
MRPC normal mode requires the host to read the MRPC command status and
output data from BAR. This results in high latency responses from the
Memory Read TLP and potential Completion Timeout (CTO).
Add support for MRPC DMA mode, including related macro definitions and data
structures and code to:
* Retrieve MRPC DMA mode version from adapter firmware
* Allocate DMA buffer, register ISR, and enable DMA during init
* Check MRPC execution status and get execution results from DMA buffer
* Release DMA buffer and disable DMA function when unloading module
MRPC DMA mode is a new feature of firmware, and the driver will fall back
to MRPC normal mode if there is no support in the legacy firmware.
Add a module parameter, "use_dma_mrpc", to select between MRPC DMA mode and
MRPC normal mode. Since the driver automatically detects DMA support in
the firmware, this parameter is just for debugging and testing.
Include <linux/io-64-nonatomic-lo-hi.h> so that readq/writeq is replaced by
two readl/writel on systems that do not support it.
Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com>
[bhelgaas: changelog, simplify dma_ver check]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
Diffstat (limited to 'include/linux/switchtec.h')
| -rw-r--r-- | include/linux/switchtec.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/linux/switchtec.h b/include/linux/switchtec.h index ab400af6f0ce..eee0412bdf4b 100644 --- a/include/linux/switchtec.h +++ b/include/linux/switchtec.h @@ -29,6 +29,7 @@ #define SWITCHTEC_EVENT_EN_IRQ BIT(3) #define SWITCHTEC_EVENT_FATAL BIT(4) +#define SWITCHTEC_DMA_MRPC_EN BIT(0) enum { SWITCHTEC_GAS_MRPC_OFFSET = 0x0000, SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000, @@ -46,6 +47,10 @@ struct mrpc_regs { u32 cmd; u32 status; u32 ret_value; + u32 dma_en; + u64 dma_addr; + u32 dma_vector; + u32 dma_ver; } __packed; enum mrpc_status { @@ -342,6 +347,14 @@ struct pff_csr_regs { struct switchtec_ntb; +struct dma_mrpc_output { + u32 status; + u32 cmd_id; + u32 rtn_code; + u32 output_size; + u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; +}; + struct switchtec_dev { struct pci_dev *pdev; struct device dev; @@ -381,6 +394,9 @@ struct switchtec_dev { u8 link_event_count[SWITCHTEC_MAX_PFF_CSR]; struct switchtec_ntb *sndev; + + struct dma_mrpc_output *dma_mrpc; + dma_addr_t dma_mrpc_dma_addr; }; static inline struct switchtec_dev *to_stdev(struct device *dev) |