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authorLinus Torvalds <torvalds@linux-foundation.org>2018-06-27 09:53:53 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2018-06-27 09:53:53 -0700
commitf8a78bdb5116a703e583b995b2d2211d5db634df (patch)
treeac1be2eae1d5bd59c160a915c809e0942438d900 /drivers
parent22c3b1521aedb4732a9dba7d4d861b7fbb4203f6 (diff)
parent86676c4685f774d818f7a6c401c925bbf2a92903 (diff)
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "A handful of fixes, nothing really concerning and most touching devicetree files for various platforms. I also regenerated the shared multiplatform defconfigs; they have drifted quite a bit due to Kconfig changes and reordering, and several platform maintainers tried doing the same which resulted in a lot of conflict pain -- this way we get everybody onto the same base for next merge window" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (31 commits) arm64: dts: uniphier: fix widget name of headphone for LD11/LD20 boards ARM: dts: Fix SPI node for Arria10 arm64: dts: stratix10: Fix SPI nodes for Stratix10 qcom: cmd-db: enforce CONFIG_OF_RESERVED_MEM dependency ARM: Always build secure_cntvoff.S on ARM V7 to fix shmobile !SMP build ARM: multi_v7_defconfig: renormalize based on recent additions arm64: defconfig: renormalize based on recent additions arm64: dts: msm8916: fix Coresight ETF graph connections arm64: dts: apq8096-db820c: disable uart0 by default ARM: dts: imx6sx: fix irq for pcie bridge arm64: dts: Stingray: Fix I2C controller interrupt type arm64: dts: ns2: Fix PCIe controller interrupt type arm64: dts: ns2: Fix I2C controller interrupt type arm64: dts: specify 1.8V EMMC capabilities for bcm958742t arm64: dts: specify 1.8V EMMC capabilities for bcm958742k ARM: dts: Cygnus: Fix PCIe controller interrupt type ARM: dts: Cygnus: Fix I2C controller interrupt type ARM: dts: BCM5301x: Fix i2c controller interrupt type ARM: dts: HR2: Fix interrupt types for i2c and PCIe ARM: dts: NSP: Fix PCIe controllers interrupt types ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/soc/imx/gpcv2.c13
-rw-r--r--drivers/soc/qcom/Kconfig3
-rw-r--r--drivers/soc/renesas/rcar-sysc.c35
3 files changed, 40 insertions, 11 deletions
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index f4e3bd40c72e..6ef18cf8f243 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -39,10 +39,15 @@
#define GPC_M4_PU_PDN_FLG 0x1bc
-
-#define PGC_MIPI 4
-#define PGC_PCIE 5
-#define PGC_USB_HSIC 8
+/*
+ * The PGC offset values in Reference Manual
+ * (Rev. 1, 01/2018 and the older ones) GPC chapter's
+ * GPC_PGC memory map are incorrect, below offset
+ * values are from design RTL.
+ */
+#define PGC_MIPI 16
+#define PGC_PCIE 17
+#define PGC_USB_HSIC 20
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 9dc02f390ba3..5856e792d09c 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -5,7 +5,8 @@ menu "Qualcomm SoC drivers"
config QCOM_COMMAND_DB
bool "Qualcomm Command DB"
- depends on (ARCH_QCOM && OF) || COMPILE_TEST
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on OF_RESERVED_MEM
help
Command DB queries shared memory by key string for shared system
resources. Platform drivers that require to set state of a shared
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index 95120acc4d80..50d03d8b4f9a 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -194,11 +194,12 @@ static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
static bool has_cpg_mstp;
-static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
+static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
{
struct generic_pm_domain *genpd = &pd->genpd;
const char *name = pd->genpd.name;
struct dev_power_governor *gov = &simple_qos_governor;
+ int error;
if (pd->flags & PD_CPU) {
/*
@@ -251,7 +252,11 @@ static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
rcar_sysc_power_up(&pd->ch);
finalize:
- pm_genpd_init(genpd, gov, false);
+ error = pm_genpd_init(genpd, gov, false);
+ if (error)
+ pr_err("Failed to init PM domain %s: %d\n", name, error);
+
+ return error;
}
static const struct of_device_id rcar_sysc_matches[] __initconst = {
@@ -375,6 +380,9 @@ static int __init rcar_sysc_pd_init(void)
pr_debug("%pOF: syscier = 0x%08x\n", np, syscier);
iowrite32(syscier, base + SYSCIER);
+ /*
+ * First, create all PM domains
+ */
for (i = 0; i < info->num_areas; i++) {
const struct rcar_sysc_area *area = &info->areas[i];
struct rcar_sysc_pd *pd;
@@ -397,14 +405,29 @@ static int __init rcar_sysc_pd_init(void)
pd->ch.isr_bit = area->isr_bit;
pd->flags = area->flags;
- rcar_sysc_pd_setup(pd);
- if (area->parent >= 0)
- pm_genpd_add_subdomain(domains->domains[area->parent],
- &pd->genpd);
+ error = rcar_sysc_pd_setup(pd);
+ if (error)
+ goto out_put;
domains->domains[area->isr_bit] = &pd->genpd;
}
+ /*
+ * Second, link all PM domains to their parents
+ */
+ for (i = 0; i < info->num_areas; i++) {
+ const struct rcar_sysc_area *area = &info->areas[i];
+
+ if (!area->name || area->parent < 0)
+ continue;
+
+ error = pm_genpd_add_subdomain(domains->domains[area->parent],
+ domains->domains[area->isr_bit]);
+ if (error)
+ pr_warn("Failed to add PM subdomain %s to parent %u\n",
+ area->name, area->parent);
+ }
+
error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
out_put: