diff options
| author | Ville Syrjala <syrjala@sci.fi> | 2007-05-08 00:39:45 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-08 11:15:32 -0700 |
| commit | b4e124c138558a0cff51398ddff9a8e44ed0b529 (patch) | |
| tree | e1a639605283cc9b55d51d81fae54e330a84e34c /drivers | |
| parent | 94f45bcd1c29e773b6bf189ef7b9a3437d016320 (diff) | |
atyfb: reorganize clock init
Reorganize atyfb clock init code so command line clock overrides are effective
for all chips. The old code would silently ignore some of the command line
clock overrides with some chips.
Signed-off-by: Antonino Daplas <adaplas@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/aty/atyfb_base.c | 32 |
1 files changed, 18 insertions, 14 deletions
diff --git a/drivers/video/aty/atyfb_base.c b/drivers/video/aty/atyfb_base.c index a92e02aa8d18..b61ab3b4c922 100644 --- a/drivers/video/aty/atyfb_base.c +++ b/drivers/video/aty/atyfb_base.c @@ -2297,20 +2297,6 @@ static int __devinit aty_init(struct fb_info *info) par->pll_limits.xclk = 53; } #endif - if (pll) - par->pll_limits.pll_max = pll; - if (mclk) - par->pll_limits.mclk = mclk; - if (xclk) - par->pll_limits.xclk = xclk; - - aty_calc_mem_refresh(par, par->pll_limits.xclk); - par->pll_per = 1000000/par->pll_limits.pll_max; - par->mclk_per = 1000000/par->pll_limits.mclk; - par->xclk_per = 1000000/par->pll_limits.xclk; - - par->ref_clk_per = 1000000000000ULL / 14318180; - xtal = "14.31818"; #ifdef CONFIG_FB_ATY_GX if (!M64_HAS(INTEGRATED)) { @@ -2392,7 +2378,25 @@ static int __devinit aty_init(struct fb_info *info) if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM) par->pll_limits.mclk = 63; } +#endif + /* Allow command line to override clocks. */ + if (pll) + par->pll_limits.pll_max = pll; + if (mclk) + par->pll_limits.mclk = mclk; + if (xclk) + par->pll_limits.xclk = xclk; + + aty_calc_mem_refresh(par, par->pll_limits.xclk); + par->pll_per = 1000000/par->pll_limits.pll_max; + par->mclk_per = 1000000/par->pll_limits.mclk; + par->xclk_per = 1000000/par->pll_limits.xclk; + + par->ref_clk_per = 1000000000000ULL / 14318180; + xtal = "14.31818"; + +#ifdef CONFIG_FB_ATY_CT if (M64_HAS(GTB_DSP)) { u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); |