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authorGil Fine <gil.fine@intel.com>2022-09-29 12:49:48 +0300
committerMika Westerberg <mika.westerberg@linux.intel.com>2023-06-16 09:53:28 +0300
commit6e19d48ea0d8aeee5688e5718cf2143d281864f3 (patch)
treed72c64c3b5923c8bdde45dd1bd0adfa2d71066e3 /drivers/thunderbolt/usb4.c
parent14200a2631dd1f041201985e2a757d2d06ba2524 (diff)
thunderbolt: Enable USB4 v2 PCIe TLP/DLLP extended encapsulation
USB4 v2 spec introduces modified encapsulation of PCIe TLP and DLLP packets. This improves the PCIe tunneled traffic usage by reducing overhead. Enable this if both sides of the link support it. Signed-off-by: Gil Fine <gil.fine@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/thunderbolt/usb4.c')
-rw-r--r--drivers/thunderbolt/usb4.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/thunderbolt/usb4.c b/drivers/thunderbolt/usb4.c
index 9f5a98347bee..302d8d3fbd5a 100644
--- a/drivers/thunderbolt/usb4.c
+++ b/drivers/thunderbolt/usb4.c
@@ -2796,3 +2796,34 @@ int usb4_dp_port_requested_bw(struct tb_port *port)
return (val & ADP_DP_CS_8_REQUESTED_BW_MASK) * granularity;
}
+
+/**
+ * usb4_pci_port_set_ext_encapsulation() - Enable/disable extended encapsulation
+ * @port: PCIe adapter
+ * @enable: Enable/disable extended encapsulation
+ *
+ * Enables or disables extended encapsulation used in PCIe tunneling. Caller
+ * needs to make sure both adapters support this before enabling. Returns %0 on
+ * success and negative errno otherwise.
+ */
+int usb4_pci_port_set_ext_encapsulation(struct tb_port *port, bool enable)
+{
+ u32 val;
+ int ret;
+
+ if (!tb_port_is_pcie_up(port) && !tb_port_is_pcie_down(port))
+ return -EINVAL;
+
+ ret = tb_port_read(port, &val, TB_CFG_PORT,
+ port->cap_adap + ADP_PCIE_CS_1, 1);
+ if (ret)
+ return ret;
+
+ if (enable)
+ val |= ADP_PCIE_CS_1_EE;
+ else
+ val &= ~ADP_PCIE_CS_1_EE;
+
+ return tb_port_write(port, &val, TB_CFG_PORT,
+ port->cap_adap + ADP_PCIE_CS_1, 1);
+}