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authorTakashi Iwai <tiwai@suse.de>2017-01-25 22:11:17 +0100
committerTakashi Iwai <tiwai@suse.de>2017-01-25 22:11:17 +0100
commite1a063f43a5e0435ecf8a2b6d42e10e20e8caf61 (patch)
tree7329fb15e57917a503c859f7266fcd034728bd54 /drivers/pci/probe.c
parent9eb5d0e635ebe2f227d591e531d48c6f01c0dd78 (diff)
parent0369d6315bc2bc56da2a2b15c8074b889096a47e (diff)
Merge branch 'topic/intel-lpe-audio' into for-next
Diffstat (limited to 'drivers/pci/probe.c')
-rw-r--r--drivers/pci/probe.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index e164b5c9f0f0..204960e70333 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1169,6 +1169,7 @@ void set_pcie_port_type(struct pci_dev *pdev)
pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
if (!pos)
return;
+
pdev->pcie_cap = pos;
pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
pdev->pcie_flags_reg = reg16;
@@ -1176,13 +1177,14 @@ void set_pcie_port_type(struct pci_dev *pdev)
pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
/*
- * A Root Port is always the upstream end of a Link. No PCIe
- * component has two Links. Two Links are connected by a Switch
- * that has a Port on each Link and internal logic to connect the
- * two Ports.
+ * A Root Port or a PCI-to-PCIe bridge is always the upstream end
+ * of a Link. No PCIe component has two Links. Two Links are
+ * connected by a Switch that has a Port on each Link and internal
+ * logic to connect the two Ports.
*/
type = pci_pcie_type(pdev);
- if (type == PCI_EXP_TYPE_ROOT_PORT)
+ if (type == PCI_EXP_TYPE_ROOT_PORT ||
+ type == PCI_EXP_TYPE_PCIE_BRIDGE)
pdev->has_secondary_link = 1;
else if (type == PCI_EXP_TYPE_UPSTREAM ||
type == PCI_EXP_TYPE_DOWNSTREAM) {