diff options
| author | Fabio Estevam <fabio.estevam@nxp.com> | 2018-08-28 17:02:40 -0300 |
|---|---|---|
| committer | Lee Jones <lee.jones@linaro.org> | 2018-10-23 08:58:34 +0100 |
| commit | 55143439b7b501882bea9d95a54adfe00ffc79a3 (patch) | |
| tree | 3ecb441aac317c31f55ddc5643d83df344cf5f89 /drivers/mfd/mc13xxx-core.c | |
| parent | 6360e40f421fba0a11bbabaa211c9c22c5cf5e61 (diff) | |
mfd: mc13xxx-core: Fix PMIC shutdown when reading ADC values
When trying to read any MC13892 ADC channel on a imx51-babbage board:
The MC13892 PMIC shutdowns completely.
After debugging this issue and comparing the MC13892 and MC13783
initializations done in the vendor kernel, it was noticed that the
CHRGRAWDIV bit of the ADC0 register was not being set.
This bit is set by default after power on, but the driver was
clearing it.
After setting this bit it is possible to read the ADC values correctly.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'drivers/mfd/mc13xxx-core.c')
| -rw-r--r-- | drivers/mfd/mc13xxx-core.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c index c63e331738c1..f475e848252f 100644 --- a/drivers/mfd/mc13xxx-core.c +++ b/drivers/mfd/mc13xxx-core.c @@ -276,7 +276,8 @@ int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode, mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0); - adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2; + adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2 | + MC13XXX_ADC0_CHRGRAWDIV; adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC; /* |