diff options
author | Marvin Lin <milkfafa@gmail.com> | 2023-01-11 17:32:45 +0800 |
---|---|---|
committer | Borislav Petkov (AMD) <bp@alien8.de> | 2023-06-12 15:14:10 +0200 |
commit | d244c610f1d9a9d2976192c1d7e114a59fba02e0 (patch) | |
tree | 37fe5eb262a547598649851a1ff33a4b39f736e7 /drivers/edac/Kconfig | |
parent | a053b7e579bdc2d0d66ee263a76214f6f1f89549 (diff) |
EDAC/npcm: Add NPCM memory controller driver
Add driver for memory controller present on Nuvoton NPCM SoCs. The
memory controller supports single bit error correction and double bit
error detection.
Signed-off-by: Marvin Lin <milkfafa@gmail.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230111093245.318745-4-milkfafa@gmail.com
Diffstat (limited to 'drivers/edac/Kconfig')
-rw-r--r-- | drivers/edac/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 68f576700911..110e99b86a66 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -550,4 +550,15 @@ config EDAC_ZYNQMP Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be built as a module. In that case it will be called zynqmp_edac. +config EDAC_NPCM + tristate "Nuvoton NPCM DDR Memory Controller" + depends on (ARCH_NPCM || COMPILE_TEST) + help + Support for error detection and correction on the Nuvoton NPCM DDR + memory controller. + + The memory controller supports single bit error correction, double bit + error detection (in-line ECC in which a section 1/8th of the memory + device used to store data is used for ECC storage). + endif # EDAC |