diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-10-05 11:32:59 +0900 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-11-14 10:04:07 -0800 |
| commit | 67affb78a4e4feb837953e3434c8402a5c3b272f (patch) | |
| tree | 70b229c8ac60c2e509cd09df75a0b978d8224f0e /drivers/clk | |
| parent | 3a5dfa7d78976fd712b63b3db4357d94dcd3c5ba (diff) | |
clk: uniphier: fix DAPLL2 clock rate of Pro5
The parent of DAPLL2 should be DAPLL1. Fix the clock connection.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/uniphier/clk-uniphier-sys.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 0e396f3da526..bffe095e603a 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -123,7 +123,7 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */ UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */ - UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */ + UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), UNIPHIER_PRO5_SYS_CLK_NAND(2), |