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authorMarek Szyprowski <m.szyprowski@samsung.com>2018-09-12 15:16:41 +0200
committerSylwester Nawrocki <snawrocki@kernel.org>2018-10-05 13:36:36 +0200
commitdefadcc956cacfb36ecf9902bd56dc5a14fdec49 (patch)
tree2df57999d6c2d5c8e56326813aff4ab02e74cdc7 /drivers/clk/samsung
parentfa34efff75d4a853551c8154e0685d44a7a6a6aa (diff)
clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend
All sclk_uart clocks in TOP CMU have to be kept enabled for suspend/resume cycle, otherwise TM2(e) boards hangs before entering the suspend mode. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 13384f4911c7..751e2c4fb65b 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -180,6 +180,8 @@ static const unsigned long top_clk_regs[] __initconst = {
static const struct samsung_clk_reg_dump top_suspend_regs[] = {
/* force all aclk clocks enabled */
{ ENABLE_ACLK_TOP, 0x67ecffed },
+ /* force all sclk_uart clocks enabled */
+ { ENABLE_SCLK_TOP_PERIC, 0x38 },
/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
{ ISP_PLL_CON0, 0x85cc0502 },
/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */