diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-19 12:21:40 +0100 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2018-03-13 10:09:47 +0100 |
| commit | c77de0e5c95a249fd2d4105dbc619f436ec96345 (patch) | |
| tree | 7e13012bbe553dca5de5db6f542c81ba1da41a1c /drivers/clk/meson/axg.c | |
| parent | 8289aafa4f361050b05f77a35d3167259530a473 (diff) | |
clk: meson: add gp0 frac parameter for axg and gxl
Add the frac parameter for the gp0 pll of the axg and gxl.
This allows to achieve rates between the fixed settings provided
by the table.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.c')
| -rw-r--r-- | drivers/clk/meson/axg.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 4f13929cd594..892572a2d70f 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -193,7 +193,7 @@ static const struct pll_rate_table axg_gp0_pll_rate_table[] = { }; const struct reg_sequence axg_gp0_init_regs[] = { - { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 }, + { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, @@ -218,6 +218,11 @@ static struct clk_regmap axg_gp0_pll = { .shift = 16, .width = 2, }, + .frac = { + .reg_off = HHI_GP0_PLL_CNTL1, + .shift = 0, + .width = 10, + }, .l = { .reg_off = HHI_GP0_PLL_CNTL, .shift = 31, |