diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2023-02-28 19:26:55 -0500 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-03-06 14:41:20 -0800 |
| commit | 89dc65a7cc8a119c395c0931b12d7a514f9d2bcc (patch) | |
| tree | 3afa1bfee774f1d1173abb0c469909d3854b1049 /drivers/clk/clk-k210.c | |
| parent | 26243872fe26ec0df7d81766253d00213990e382 (diff) | |
clk: k210: remove an implicit 64-bit division
The K210 clock driver depends on SOC_CANAAN, which is only selectable
when !MMU on RISC-V. !MMU is not possible on 32-bit yet, but patches
have been sent for its enabling. The kernel test robot reported this
implicit 64-bit division there.
Replace the implicit division with an explicit one.
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/linux-riscv/202301201538.zNlqgE4L-lkp@intel.com/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Link: https://lore.kernel.org/r/20230301002657.352637-2-Mr.Bossman075@gmail.com
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-k210.c')
| -rw-r--r-- | drivers/clk/clk-k210.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c index 67a7cb3503c3..4eed667eddaf 100644 --- a/drivers/clk/clk-k210.c +++ b/drivers/clk/clk-k210.c @@ -495,7 +495,7 @@ static unsigned long k210_pll_get_rate(struct clk_hw *hw, f = FIELD_GET(K210_PLL_CLKF, reg) + 1; od = FIELD_GET(K210_PLL_CLKOD, reg) + 1; - return (u64)parent_rate * f / (r * od); + return div_u64((u64)parent_rate * f, r * od); } static const struct clk_ops k210_pll_ops = { |