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authorKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>2023-09-24 20:31:01 +0200
committerBjorn Andersson <andersson@kernel.org>2023-12-02 16:48:46 -0800
commit94da379dba88c4cdd562bad21c9ba5656e5ed5df (patch)
tree91ffdce2a68085ae977eeeed1eca36b366fcf785 /arch
parentbded0924f6a424eb9bf675759aa90741940e5628 (diff)
ARM: dts: qcom: sdx65: correct PCIe EP phy-names
Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy": arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected Fixes: 9c0bb38414a4 ("ARM: dts: qcom: sdx65: Add support for PCIe EP") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230924183103.49487-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/qcom/qcom-sdx65.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index 726755c4f8a3..ab492c47baaa 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -333,7 +333,7 @@
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie_phy>;
- phy-names = "pcie-phy";
+ phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;