diff options
| author | Len Brown <len.brown@intel.com> | 2022-05-31 17:29:13 -1000 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2022-07-28 14:23:26 -0400 |
| commit | 4af184ee8b2c0a69a038483ba605510203bf015b (patch) | |
| tree | 9e429bb224d154170b00052af946ffe772ca996c /arch | |
| parent | 5d6228452c008d1186e8d6a5ef3079e608e7a888 (diff) | |
tools/power turbostat: dump secondary Turbo-Ratio-Limit
Intel Performance Hybrid processors have a 2nd MSR
describing the turbo limits enforced on the Ecores.
Note, TRL and Secondary-TRL are usually R/O information,
but on overclock-capable parts, they can be written.
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index cc615be27a54..1ac0f9bf4b90 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -388,6 +388,7 @@ #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D +#define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 |