diff options
| author | Joerg Roedel <jroedel@suse.de> | 2021-12-02 16:32:24 +0100 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2021-12-06 09:38:48 +0100 |
| commit | f154f290855b070cc94dd44ad253c0ef8a9337bb (patch) | |
| tree | 804830bc075803ec0553bb866cf2612f1f504447 /arch/x86/mm | |
| parent | 9de4999050b5f2e847c84372c6a1aa1fe32bb269 (diff) | |
x86/mm/64: Flush global TLB on boot and AP bringup
The AP bringup code uses the trampoline_pgd page-table which
establishes global mappings in the user range of the address space.
Flush the global TLB entries after the indentity mappings are removed so
no stale entries remain in the TLB.
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20211202153226.22946-3-joro@8bytes.org
Diffstat (limited to 'arch/x86/mm')
| -rw-r--r-- | arch/x86/mm/tlb.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 59ba2968af1b..1e6513f95133 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1148,7 +1148,7 @@ void flush_tlb_one_user(unsigned long addr) */ STATIC_NOPV void native_flush_tlb_global(void) { - unsigned long cr4, flags; + unsigned long flags; if (static_cpu_has(X86_FEATURE_INVPCID)) { /* @@ -1168,11 +1168,7 @@ STATIC_NOPV void native_flush_tlb_global(void) */ raw_local_irq_save(flags); - cr4 = this_cpu_read(cpu_tlbstate.cr4); - /* toggle PGE */ - native_write_cr4(cr4 ^ X86_CR4_PGE); - /* write old PGE again and flush TLBs */ - native_write_cr4(cr4); + __native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4)); raw_local_irq_restore(flags); } |