diff options
| author | Justin Swartz <justin.swartz@risingedge.co.za> | 2024-03-16 06:54:39 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-04-15 10:23:37 +0200 |
| commit | 6f04e524442ed4e258ae9c3e68eddf9c901e438c (patch) | |
| tree | d9c4537b450ea2e026bf9d7065e9512975dace81 /arch/mips/boot | |
| parent | a76a20f9e133dcd70d1cedd2705c58dbee33bb36 (diff) | |
mips: dts: ralink: mt7621: reorder ethernet node attributes and kids
Rearrange attributes and descendents declared under the
ethernet node, recursively, to follow the DTS style guide.
Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
Reviewed-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/boot')
| -rw-r--r-- | arch/mips/boot/dts/ralink/mt7621.dtsi | 88 |
1 files changed, 48 insertions, 40 deletions
diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 8aa9eba686d5..f6418201bc10 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -364,46 +364,22 @@ compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; - clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>; - clock-names = "fe", "ethif"; - #address-cells = <1>; #size-cells = <0>; - resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>; - reset-names = "fe", "eth"; + clock-names = "fe", "ethif"; + clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>; interrupt-parent = <&gic>; interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; - mediatek,ethsys = <&sysc>; - pinctrl-names = "default"; pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "rgmii"; + reset-names = "fe", "eth"; + resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; + mediatek,ethsys = <&sysc>; mdio: mdio-bus { #address-cells = <1>; @@ -412,73 +388,105 @@ switch0: switch@1f { compatible = "mediatek,mt7621"; reg = <0x1f>; - mediatek,mcm; - resets = <&sysc MT7621_RST_MCM>; - reset-names = "mcm"; - interrupt-controller; + #interrupt-cells = <1>; + interrupt-controller; interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; + reset-names = "mcm"; + resets = <&sysc MT7621_RST_MCM>; + + mediatek,mcm; + ports { #address-cells = <1>; #size-cells = <0>; port@0 { - status = "disabled"; reg = <0>; label = "swp0"; + status = "disabled"; }; port@1 { - status = "disabled"; reg = <1>; label = "swp1"; + status = "disabled"; }; port@2 { - status = "disabled"; reg = <2>; label = "swp2"; + status = "disabled"; }; port@3 { - status = "disabled"; reg = <3>; label = "swp3"; + status = "disabled"; }; port@4 { - status = "disabled"; reg = <4>; label = "swp4"; + status = "disabled"; }; port@5 { reg = <5>; + ethernet = <&gmac1>; phy-mode = "rgmii"; fixed-link { - speed = <1000>; full-duplex; pause; + speed = <1000>; }; }; port@6 { reg = <6>; + ethernet = <&gmac0>; phy-mode = "trgmii"; fixed-link { - speed = <1000>; full-duplex; pause; + speed = <1000>; }; }; }; }; }; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-mode = "trgmii"; + + fixed-link { + full-duplex; + pause; + speed = <1000>; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + + phy-mode = "rgmii"; + + fixed-link { + full-duplex; + pause; + speed = <1000>; + }; + }; + }; pcie: pcie@1e140000 { |