diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-05-20 09:09:52 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-05-30 09:37:09 +0900 |
| commit | 33df2753637b2d59adcfd13c35761ff13ff1c673 (patch) | |
| tree | b1c6acf9d1cd4a523ef31e59664781738b70f100 /arch/arm/boot | |
| parent | 79c530ed4dd374e51f3c8ff75134a1da201952b7 (diff) | |
ARM: dts: emev2: Fix W=1 dtc warnings
Warning (unit_address_vs_reg): Node /clocks@e0110000/iic0_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/iic0_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/iic1_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/iic1_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usia_u0_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u1_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u2_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u3_sclkdiv has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usia_u0_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u1_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u2_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u3_sclk has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /clocks@e0110000/sti_sclk has a reg or ranges property, but no unit name
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/emev2.dtsi | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index bcce6f50c93d..cd119400f440 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -69,25 +69,25 @@ clock-frequency = <32768>; #clock-cells = <0>; }; - iic0_sclkdiv: iic0_sclkdiv { + iic0_sclkdiv: iic0_sclkdiv@624,0 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x624 0>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - iic0_sclk: iic0_sclk { + iic0_sclk: iic0_sclk@48c,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x48c 1>; clocks = <&iic0_sclkdiv>; #clock-cells = <0>; }; - iic1_sclkdiv: iic1_sclkdiv { + iic1_sclkdiv: iic1_sclkdiv@624,16 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x624 16>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - iic1_sclk: iic1_sclk { + iic1_sclk: iic1_sclk@490,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x490 1>; clocks = <&iic1_sclkdiv>; @@ -100,55 +100,55 @@ clock-mult = <7000>; #clock-cells = <0>; }; - usia_u0_sclkdiv: usia_u0_sclkdiv { + usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x610 0>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - usib_u1_sclkdiv: usib_u1_sclkdiv { + usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x65c 0>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - usib_u2_sclkdiv: usib_u2_sclkdiv { + usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x65c 16>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - usib_u3_sclkdiv: usib_u3_sclkdiv { + usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x660 0>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - usia_u0_sclk: usia_u0_sclk { + usia_u0_sclk: usia_u0_sclk@4a0,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x4a0 1>; clocks = <&usia_u0_sclkdiv>; #clock-cells = <0>; }; - usib_u1_sclk: usib_u1_sclk { + usib_u1_sclk: usib_u1_sclk@4b8,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x4b8 1>; clocks = <&usib_u1_sclkdiv>; #clock-cells = <0>; }; - usib_u2_sclk: usib_u2_sclk { + usib_u2_sclk: usib_u2_sclk@4bc,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x4bc 1>; clocks = <&usib_u2_sclkdiv>; #clock-cells = <0>; }; - usib_u3_sclk: usib_u3_sclk { + usib_u3_sclk: usib_u3_sclk@4c0,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x4c0 1>; clocks = <&usib_u3_sclkdiv>; #clock-cells = <0>; }; - sti_sclk: sti_sclk { + sti_sclk: sti_sclk@528,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x528 1>; clocks = <&c32ki>; |