diff options
| author | Vineet Gupta <vgupta@synopsys.com> | 2013-05-28 15:24:30 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2013-06-22 19:23:23 +0530 |
| commit | 1898a959b7512fcf6fa9f436ac8c403fab7255c3 (patch) | |
| tree | e990d920414c458af317afb08f53c7f9e05404b3 /arch/arc | |
| parent | 3ebedbb2fdf730b7e5e2417dbd37faee6304bfb5 (diff) | |
ARC: Entry Handler tweaks: Avoid hardcoded LIMMS for ECR values
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 5 | ||||
| -rw-r--r-- | arch/arc/kernel/entry.S | 15 |
2 files changed, 14 insertions, 6 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 6addeec34a7c..122e9af46824 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -68,6 +68,11 @@ #define ECR_C_PROTV_XCHG 0x03 #define ECR_C_PROTV_MISALIG_DATA 0x04 +#define ECR_C_BIT_PROTV_MISALIG_DATA 10 + +/* Machine Check Cause Code Values */ +#define ECR_C_MCHK_DUP_TLB 0x01 + /* DTLB Miss Exception Cause Code Values */ #define ECR_C_BIT_DTLB_LD_MISS 8 #define ECR_C_BIT_DTLB_ST_MISS 9 diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S index 53655bf4c9d7..b4a96144430d 100644 --- a/arch/arc/kernel/entry.S +++ b/arch/arc/kernel/entry.S @@ -321,7 +321,10 @@ ARC_ENTRY EV_MachineCheck lr r1, [efa] mov r2, sp - brne r0, 0x200100, 1f + lsr r3, r0, 8 + bmsk r3, r3, 7 + brne r3, ECR_C_MCHK_DUP_TLB, 1f + bl do_tlb_overlap_fault b ret_from_exception @@ -368,11 +371,11 @@ ARC_ENTRY EV_TLBProtV ;------ (5) Type of Protection Violation? ---------- ; ; ProtV Hardware Exception is triggered for Access Faults of 2 types - ; -Access Violaton (WRITE to READ ONLY Page) - for linux COW - ; -Unaligned Access (READ/WRITE on odd boundary) + ; -Access Violaton : 00_23_(00|01|02|03)_00 + ; x r w r+w + ; -Unaligned Access : 00_23_04_00 ; - cmp r2, 0x230400 ; Misaligned data access ? - beq 4f + bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f ;========= (6a) Access Violation Processing ======== mov r0, sp ; pt_regs @@ -542,7 +545,7 @@ ARC_ENTRY EV_Trap ;------- (4) What caused the Trap -------------- lr r12, [ecr] - and.f 0, r12, ECR_PARAM_MASK + bmsk.f 0, r12, 7 bnz trap_with_param ; ======= (5a) Trap is due to System Call ======== |