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authorBartosz Golaszewski <bartosz.golaszewski@linaro.org>2024-08-07 15:31:43 +0200
committerBjorn Andersson <andersson@kernel.org>2024-08-14 21:58:21 -0500
commit4f79d0deae37c298bbce5142937080ff5cc61a25 (patch)
tree12dce3ece2ad48c7b8cdbdcb9959a18cb0bce96d
parentc46eef29907bc1644e0ded4b99bbd0be5ccde9a7 (diff)
arm64: dts: qcom: sa8775p: add CPU idle states
Add CPU idle-state nodes and power-domains to the .dtsi for SA8775P. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240807-sa8775p-idle-states-v1-1-f2b5fcdfa0b0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--arch/arm64/boot/dts/qcom/sa8775p.dtsi115
1 files changed, 115 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 6dc1f518e035..801e8a92359d 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -220,6 +220,48 @@
};
};
};
+
+ idle-states {
+ entry-method = "psci";
+
+ GOLD_CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-power-collapse";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <549>;
+ exit-latency-us = <901>;
+ min-residency-us = <1774>;
+ local-timer-stop;
+ };
+
+ GOLD_RAIL_CPU_SLEEP_0: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <702>;
+ exit-latency-us = <1061>;
+ min-residency-us = <4488>;
+ local-timer-stop;
+ };
+ };
+
+ domain-idle-states {
+ CLUSTER_SLEEP_GOLD: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <2752>;
+ exit-latency-us = <3048>;
+ min-residency-us = <6118>;
+ };
+
+ CLUSTER_SLEEP_APSS_RSC_PC: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x42000144>;
+ entry-latency-us = <3263>;
+ exit-latency-us = <6562>;
+ min-residency-us = <9987>;
+ };
+ };
};
dummy-sink {
@@ -349,6 +391,79 @@
psci {
compatible = "arm,psci-1.0";
method = "smc";
+
+ CPU_PD0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_0_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>,
+ <&GOLD_RAIL_CPU_SLEEP_0>;
+ };
+
+ CPU_PD1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_0_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>,
+ <&GOLD_RAIL_CPU_SLEEP_0>;
+ };
+
+ CPU_PD2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_0_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>,
+ <&GOLD_RAIL_CPU_SLEEP_0>;
+ };
+
+ CPU_PD3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_0_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>,
+ <&GOLD_RAIL_CPU_SLEEP_0>;
+ };
+
+ CPU_PD4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_1_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>,
+ <&GOLD_RAIL_CPU_SLEEP_0>;
+ };
+
+ CPU_PD5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_1_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>,
+ <&GOLD_RAIL_CPU_SLEEP_0>;
+ };
+
+ CPU_PD6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_1_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>,
+ <&GOLD_RAIL_CPU_SLEEP_0>;
+ };
+
+ CPU_PD7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_1_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>,
+ <&GOLD_RAIL_CPU_SLEEP_0>;
+ };
+
+ CLUSTER_0_PD: power-domain-cluster0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_2_PD>;
+ domain-idle-states = <&CLUSTER_SLEEP_GOLD>;
+ };
+
+ CLUSTER_1_PD: power-domain-cluster1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_2_PD>;
+ domain-idle-states = <&CLUSTER_SLEEP_GOLD>;
+ };
+
+ CLUSTER_2_PD: power-domain-cluster2 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_SLEEP_APSS_RSC_PC>;
+ };
};
reserved-memory {