diff options
| author | James Morse <james.morse@arm.com> | 2022-11-30 17:16:09 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-12-01 15:53:14 +0000 |
| commit | 1ecf3dcb136320359ffd79d1ca5908e078443b6b (patch) | |
| tree | 742671e4b4c8acb8812d1bd5d706b7e64fd3aa7b | |
| parent | 0a648056d68d4049dfb5d1c36b79ad3eba0090f0 (diff) | |
arm64/sysreg: Standardise naming for ID_PFR2_EL1
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_PFR2_EL1 register have an _EL1 suffix.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-11-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 4 | ||||
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index f93f68ebdccc..155cb298c897 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -768,8 +768,8 @@ #define ID_DFR0_COPSDBG_SHIFT 4 #define ID_DFR0_COPDBG_SHIFT 0 -#define ID_PFR2_SSBS_SHIFT 4 -#define ID_PFR2_CSV3_SHIFT 0 +#define ID_PFR2_EL1_SSBS_SHIFT 4 +#define ID_PFR2_EL1_CSV3_SHIFT 0 #define MVFR0_FPROUND_SHIFT 28 #define MVFR0_FPSHVEC_SHIFT 24 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 271a82dd59d4..8009fc2e4b5e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -560,8 +560,8 @@ static const struct arm64_ftr_bits ftr_id_pfr1[] = { }; static const struct arm64_ftr_bits ftr_id_pfr2[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), ARM64_FTR_END, }; |