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authorCong Dang <cong.dang.xn@renesas.com>2024-08-01 15:39:19 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2024-08-20 09:48:24 +0200
commit120c2833b72f4bdbd67ea2cf70b9d96d1c235717 (patch)
treec5f2d3a84168fa16642af1f44e718045b3621f72
parent36932cbc3e6cc95a681568c28bfadd72d7c2e7ce (diff)
clk: renesas: r8a779h0: Add CANFD clock
Add the CANFD module clock on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/9bf71bfda338ee5411751174b03b9e870cc818e3.1722519424.git.geert+renesas@glider.be
-rw-r--r--drivers/clk/renesas/r8a779h0-cpg-mssr.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index ef707dce8400..e20c048bfa9b 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -176,6 +176,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
+ DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("csi40", 331, R8A779H0_CLK_CSI),
DEF_MOD("csi41", 400, R8A779H0_CLK_CSI),
DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),