1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
|
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) Meta Platforms, Inc. and affiliates. */
#ifndef _FBNIC_CSR_H_
#define _FBNIC_CSR_H_
#include <linux/bitops.h>
#define CSR_BIT(nr) (1u << (nr))
#define CSR_GENMASK(h, l) GENMASK(h, l)
#define DESC_BIT(nr) BIT_ULL(nr)
#define DESC_GENMASK(h, l) GENMASK_ULL(h, l)
#define PCI_DEVICE_ID_META_FBNIC_ASIC 0x0013
#define FBNIC_CLOCK_FREQ (600 * (1000 * 1000))
/* Register Definitions
*
* The registers are laid as indexes into an le32 array. As such the actual
* address is 4 times the index value. Below each register is defined as 3
* fields, name, index, and Address.
*
* Name Index Address
*************************************************************************/
/* Interrupt Registers */
#define FBNIC_CSR_START_INTR 0x00000 /* CSR section delimiter */
#define FBNIC_INTR_STATUS(n) (0x00000 + (n)) /* 0x00000 + 4*n */
#define FBNIC_INTR_STATUS_CNT 8
#define FBNIC_INTR_MASK(n) (0x00008 + (n)) /* 0x00020 + 4*n */
#define FBNIC_INTR_MASK_CNT 8
#define FBNIC_INTR_SET(n) (0x00010 + (n)) /* 0x00040 + 4*n */
#define FBNIC_INTR_SET_CNT 8
#define FBNIC_INTR_CLEAR(n) (0x00018 + (n)) /* 0x00060 + 4*n */
#define FBNIC_INTR_CLEAR_CNT 8
#define FBNIC_INTR_SW_STATUS(n) (0x00020 + (n)) /* 0x00080 + 4*n */
#define FBNIC_INTR_SW_STATUS_CNT 8
#define FBNIC_INTR_SW_AC_MODE(n) (0x00028 + (n)) /* 0x000a0 + 4*n */
#define FBNIC_INTR_SW_AC_MODE_CNT 8
#define FBNIC_INTR_MASK_SET(n) (0x00030 + (n)) /* 0x000c0 + 4*n */
#define FBNIC_INTR_MASK_SET_CNT 8
#define FBNIC_INTR_MASK_CLEAR(n) (0x00038 + (n)) /* 0x000e0 + 4*n */
#define FBNIC_INTR_MASK_CLEAR_CNT 8
#define FBNIC_MAX_MSIX_VECS 256U
#define FBNIC_INTR_MSIX_CTRL(n) (0x00040 + (n)) /* 0x00100 + 4*n */
#define FBNIC_INTR_MSIX_CTRL_VECTOR_MASK CSR_GENMASK(7, 0)
#define FBNIC_INTR_MSIX_CTRL_ENABLE CSR_BIT(31)
#define FBNIC_CSR_END_INTR 0x0005f /* CSR section delimiter */
/* Interrupt MSIX Registers */
#define FBNIC_CSR_START_INTR_CQ 0x00400 /* CSR section delimiter */
#define FBNIC_INTR_CQ_REARM(n) \
(0x00400 + 4 * (n)) /* 0x01000 + 16*n */
#define FBNIC_INTR_CQ_REARM_CNT 256
#define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT CSR_GENMASK(13, 0)
#define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT_UPD_EN CSR_BIT(14)
#define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT CSR_GENMASK(28, 15)
#define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT_UPD_EN CSR_BIT(29)
#define FBNIC_INTR_CQ_REARM_INTR_RELOAD CSR_BIT(30)
#define FBNIC_INTR_CQ_REARM_INTR_UNMASK CSR_BIT(31)
#define FBNIC_CSR_END_INTR_CQ 0x007fe /* CSR section delimiter */
/* Global QM Tx registers */
#define FBNIC_CSR_START_QM_TX 0x00800 /* CSR section delimiter */
#define FBNIC_QM_TWQ_DEFAULT_META_L 0x00818 /* 0x02060 */
#define FBNIC_QM_TWQ_DEFAULT_META_H 0x00819 /* 0x02064 */
#define FBNIC_QM_TQS_CTL0 0x0081b /* 0x0206c */
#define FBNIC_QM_TQS_CTL0_LSO_TS_MASK CSR_BIT(0)
enum {
FBNIC_QM_TQS_CTL0_LSO_TS_FIRST = 0,
FBNIC_QM_TQS_CTL0_LSO_TS_LAST = 1,
};
#define FBNIC_QM_TQS_CTL0_PREFETCH_THRESH CSR_GENMASK(7, 1)
enum {
FBNIC_QM_TQS_CTL0_PREFETCH_THRESH_MIN = 16,
};
#define FBNIC_QM_TQS_CTL1 0x0081c /* 0x02070 */
#define FBNIC_QM_TQS_CTL1_MC_MAX_CREDITS CSR_GENMASK(7, 0)
#define FBNIC_QM_TQS_CTL1_BULK_MAX_CREDITS CSR_GENMASK(15, 8)
#define FBNIC_QM_TQS_MTU_CTL0 0x0081d /* 0x02074 */
#define FBNIC_QM_TQS_MTU_CTL1 0x0081e /* 0x02078 */
#define FBNIC_QM_TQS_MTU_CTL1_BULK CSR_GENMASK(13, 0)
#define FBNIC_QM_TCQ_CTL0 0x0082d /* 0x020b4 */
#define FBNIC_QM_TCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0)
#define FBNIC_QM_TCQ_CTL0_TICK_CYCLES CSR_GENMASK(26, 16)
#define FBNIC_QM_TQS_EDT_TS_RANGE 0x00849 /* 0x2124 */
#define FBNIC_QM_TNI_TDF_CTL 0x0086c /* 0x021b0 */
#define FBNIC_QM_TNI_TDF_CTL_MRRS CSR_GENMASK(1, 0)
#define FBNIC_QM_TNI_TDF_CTL_CLS CSR_GENMASK(3, 2)
#define FBNIC_QM_TNI_TDF_CTL_MAX_OT CSR_GENMASK(11, 4)
#define FBNIC_QM_TNI_TDF_CTL_MAX_OB CSR_GENMASK(23, 12)
#define FBNIC_QM_TNI_TDE_CTL 0x0086d /* 0x021b4 */
#define FBNIC_QM_TNI_TDE_CTL_MRRS CSR_GENMASK(1, 0)
#define FBNIC_QM_TNI_TDE_CTL_CLS CSR_GENMASK(3, 2)
#define FBNIC_QM_TNI_TDE_CTL_MAX_OT CSR_GENMASK(11, 4)
#define FBNIC_QM_TNI_TDE_CTL_MAX_OB CSR_GENMASK(24, 12)
#define FBNIC_QM_TNI_TDE_CTL_MRRS_1K CSR_BIT(25)
#define FBNIC_QM_TNI_TCM_CTL 0x0086e /* 0x021b8 */
#define FBNIC_QM_TNI_TCM_CTL_MPS CSR_GENMASK(1, 0)
#define FBNIC_QM_TNI_TCM_CTL_CLS CSR_GENMASK(3, 2)
#define FBNIC_QM_TNI_TCM_CTL_MAX_OT CSR_GENMASK(11, 4)
#define FBNIC_QM_TNI_TCM_CTL_MAX_OB CSR_GENMASK(23, 12)
#define FBNIC_CSR_END_QM_TX 0x00873 /* CSR section delimiter */
/* Global QM Rx registers */
#define FBNIC_CSR_START_QM_RX 0x00c00 /* CSR section delimiter */
#define FBNIC_QM_RCQ_CTL0 0x00c0c /* 0x03030 */
#define FBNIC_QM_RCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0)
#define FBNIC_QM_RCQ_CTL0_TICK_CYCLES CSR_GENMASK(26, 16)
#define FBNIC_QM_RNI_RBP_CTL 0x00c2d /* 0x030b4 */
#define FBNIC_QM_RNI_RBP_CTL_MRRS CSR_GENMASK(1, 0)
#define FBNIC_QM_RNI_RBP_CTL_CLS CSR_GENMASK(3, 2)
#define FBNIC_QM_RNI_RBP_CTL_MAX_OT CSR_GENMASK(11, 4)
#define FBNIC_QM_RNI_RBP_CTL_MAX_OB CSR_GENMASK(23, 12)
#define FBNIC_QM_RNI_RDE_CTL 0x00c2e /* 0x030b8 */
#define FBNIC_QM_RNI_RDE_CTL_MPS CSR_GENMASK(1, 0)
#define FBNIC_QM_RNI_RDE_CTL_CLS CSR_GENMASK(3, 2)
#define FBNIC_QM_RNI_RDE_CTL_MAX_OT CSR_GENMASK(11, 4)
#define FBNIC_QM_RNI_RDE_CTL_MAX_OB CSR_GENMASK(23, 12)
#define FBNIC_QM_RNI_RCM_CTL 0x00c2f /* 0x030bc */
#define FBNIC_QM_RNI_RCM_CTL_MPS CSR_GENMASK(1, 0)
#define FBNIC_QM_RNI_RCM_CTL_CLS CSR_GENMASK(3, 2)
#define FBNIC_QM_RNI_RCM_CTL_MAX_OT CSR_GENMASK(11, 4)
#define FBNIC_QM_RNI_RCM_CTL_MAX_OB CSR_GENMASK(23, 12)
#define FBNIC_CSR_END_QM_RX 0x00c34 /* CSR section delimiter */
/* TCE registers */
#define FBNIC_CSR_START_TCE 0x04000 /* CSR section delimiter */
#define FBNIC_TCE_REG_BASE 0x04000 /* 0x10000 */
#define FBNIC_TCE_LSO_CTRL 0x04000 /* 0x10000 */
#define FBNIC_TCE_LSO_CTRL_TCPF_CLR_1ST CSR_GENMASK(8, 0)
#define FBNIC_TCE_LSO_CTRL_TCPF_CLR_MID CSR_GENMASK(17, 9)
#define FBNIC_TCE_LSO_CTRL_TCPF_CLR_END CSR_GENMASK(26, 18)
#define FBNIC_TCE_LSO_CTRL_IPID_MODE_INC CSR_BIT(27)
#define FBNIC_TCE_CSO_CTRL 0x04001 /* 0x10004 */
#define FBNIC_TCE_CSO_CTRL_TCP_ZERO_CSUM CSR_BIT(0)
#define FBNIC_TCE_TXB_CTRL 0x04002 /* 0x10008 */
#define FBNIC_TCE_TXB_CTRL_LOAD CSR_BIT(0)
#define FBNIC_TCE_TXB_CTRL_TCAM_ENABLE CSR_BIT(1)
#define FBNIC_TCE_TXB_CTRL_DISABLE CSR_BIT(2)
#define FBNIC_TCE_TXB_ENQ_WRR_CTRL 0x04003 /* 0x1000c */
#define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT0 CSR_GENMASK(7, 0)
#define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT1 CSR_GENMASK(15, 8)
#define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT2 CSR_GENMASK(23, 16)
#define FBNIC_TCE_TXB_TEI_Q0_CTRL 0x04004 /* 0x10010 */
#define FBNIC_TCE_TXB_TEI_Q1_CTRL 0x04005 /* 0x10014 */
#define FBNIC_TCE_TXB_MC_Q_CTRL 0x04006 /* 0x10018 */
#define FBNIC_TCE_TXB_RX_TEI_Q_CTRL 0x04007 /* 0x1001c */
#define FBNIC_TCE_TXB_RX_BMC_Q_CTRL 0x04008 /* 0x10020 */
#define FBNIC_TCE_TXB_Q_CTRL_START CSR_GENMASK(10, 0)
#define FBNIC_TCE_TXB_Q_CTRL_SIZE CSR_GENMASK(22, 11)
#define FBNIC_TCE_TXB_TEI_DWRR_CTRL 0x04009 /* 0x10024 */
#define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)
#define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8)
#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL 0x0400a /* 0x10028 */
#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)
#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8)
#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM2 CSR_GENMASK(23, 16)
#define FBNIC_TCE_TXB_CLDR_CFG 0x0400b /* 0x1002c */
#define FBNIC_TCE_TXB_CLDR_CFG_NUM_SLOT CSR_GENMASK(5, 0)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG(n) (0x0400c + (n)) /* 0x10030 + 4*n */
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_CNT 16
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_0 CSR_GENMASK(1, 0)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_1 CSR_GENMASK(3, 2)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_2 CSR_GENMASK(5, 4)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_3 CSR_GENMASK(7, 6)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_0 CSR_GENMASK(9, 8)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_1 CSR_GENMASK(11, 10)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_2 CSR_GENMASK(13, 12)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_3 CSR_GENMASK(15, 14)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_0 CSR_GENMASK(17, 16)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_1 CSR_GENMASK(19, 18)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_2 CSR_GENMASK(21, 20)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_3 CSR_GENMASK(23, 22)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_0 CSR_GENMASK(25, 24)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_1 CSR_GENMASK(27, 26)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_2 CSR_GENMASK(29, 28)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_3 CSR_GENMASK(31, 30)
#define FBNIC_TCE_BMC_MAX_PKTSZ 0x0403a /* 0x100e8 */
#define FBNIC_TCE_BMC_MAX_PKTSZ_TX CSR_GENMASK(13, 0)
#define FBNIC_TCE_BMC_MAX_PKTSZ_RX CSR_GENMASK(27, 14)
#define FBNIC_TCE_MC_MAX_PKTSZ 0x0403b /* 0x100ec */
#define FBNIC_TCE_MC_MAX_PKTSZ_TMI CSR_GENMASK(13, 0)
#define FBNIC_TCE_SOP_PROT_CTRL 0x0403c /* 0x100f0 */
#define FBNIC_TCE_SOP_PROT_CTRL_TBI CSR_GENMASK(7, 0)
#define FBNIC_TCE_SOP_PROT_CTRL_TTI_FRM CSR_GENMASK(14, 8)
#define FBNIC_TCE_SOP_PROT_CTRL_TTI_CM CSR_GENMASK(18, 15)
#define FBNIC_TCE_DROP_CTRL 0x0403d /* 0x100f4 */
#define FBNIC_TCE_DROP_CTRL_TTI_CM_DROP_EN CSR_BIT(0)
#define FBNIC_TCE_DROP_CTRL_TTI_FRM_DROP_EN CSR_BIT(1)
#define FBNIC_TCE_DROP_CTRL_TTI_TBI_DROP_EN CSR_BIT(2)
#define FBNIC_TCE_TXB_TX_BMC_Q_CTRL 0x0404B /* 0x1012c */
#define FBNIC_TCE_TXB_BMC_DWRR_CTRL 0x0404C /* 0x10130 */
#define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)
#define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8)
#define FBNIC_TCE_TXB_TEI_DWRR_CTRL_EXT 0x0404D /* 0x10134 */
#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_EXT \
0x0404E /* 0x10138 */
#define FBNIC_TCE_TXB_BMC_DWRR_CTRL_EXT 0x0404F /* 0x1013c */
#define FBNIC_CSR_END_TCE 0x04050 /* CSR section delimiter */
/* TMI registers */
#define FBNIC_CSR_START_TMI 0x04400 /* CSR section delimiter */
#define FBNIC_TMI_SOP_PROT_CTRL 0x04400 /* 0x11000 */
#define FBNIC_CSR_END_TMI 0x0443f /* CSR section delimiter */
/* Rx Buffer Registers */
#define FBNIC_CSR_START_RXB 0x08000 /* CSR section delimiter */
enum {
FBNIC_RXB_FIFO_MC = 0,
/* Unused */
/* Unused */
FBNIC_RXB_FIFO_NET_TO_BMC = 3,
FBNIC_RXB_FIFO_HOST = 4,
/* Unused */
FBNIC_RXB_FIFO_BMC_TO_HOST = 6,
/* Unused */
FBNIC_RXB_FIFO_INDICES = 8
};
#define FBNIC_RXB_CT_SIZE(n) (0x08000 + (n)) /* 0x20000 + 4*n */
#define FBNIC_RXB_CT_SIZE_CNT 8
#define FBNIC_RXB_CT_SIZE_HEADER CSR_GENMASK(5, 0)
#define FBNIC_RXB_CT_SIZE_PAYLOAD CSR_GENMASK(11, 6)
#define FBNIC_RXB_CT_SIZE_ENABLE CSR_BIT(12)
#define FBNIC_RXB_PAUSE_DROP_CTRL 0x08008 /* 0x20020 */
#define FBNIC_RXB_PAUSE_DROP_CTRL_DROP_ENABLE CSR_GENMASK(7, 0)
#define FBNIC_RXB_PAUSE_DROP_CTRL_PAUSE_ENABLE CSR_GENMASK(15, 8)
#define FBNIC_RXB_PAUSE_DROP_CTRL_ECN_ENABLE CSR_GENMASK(23, 16)
#define FBNIC_RXB_PAUSE_DROP_CTRL_PS_ENABLE CSR_GENMASK(27, 24)
#define FBNIC_RXB_PAUSE_THLD(n) (0x08009 + (n)) /* 0x20024 + 4*n */
#define FBNIC_RXB_PAUSE_THLD_CNT 8
#define FBNIC_RXB_PAUSE_THLD_ON CSR_GENMASK(12, 0)
#define FBNIC_RXB_PAUSE_THLD_OFF CSR_GENMASK(25, 13)
#define FBNIC_RXB_DROP_THLD(n) (0x08011 + (n)) /* 0x20044 + 4*n */
#define FBNIC_RXB_DROP_THLD_CNT 8
#define FBNIC_RXB_DROP_THLD_ON CSR_GENMASK(12, 0)
#define FBNIC_RXB_DROP_THLD_OFF CSR_GENMASK(25, 13)
#define FBNIC_RXB_ECN_THLD(n) (0x0801e + (n)) /* 0x20078 + 4*n */
#define FBNIC_RXB_ECN_THLD_CNT 8
#define FBNIC_RXB_ECN_THLD_ON CSR_GENMASK(12, 0)
#define FBNIC_RXB_ECN_THLD_OFF CSR_GENMASK(25, 13)
#define FBNIC_RXB_PBUF_CFG(n) (0x08027 + (n)) /* 0x2009c + 4*n */
#define FBNIC_RXB_PBUF_CFG_CNT 8
#define FBNIC_RXB_PBUF_BASE_ADDR CSR_GENMASK(12, 0)
#define FBNIC_RXB_PBUF_SIZE CSR_GENMASK(21, 13)
#define FBNIC_RXB_DWRR_RDE_WEIGHT0 0x0802f /* 0x200bc */
#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM0 CSR_GENMASK(7, 0)
#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM1 CSR_GENMASK(15, 8)
#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM2 CSR_GENMASK(23, 16)
#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM3 CSR_GENMASK(31, 24)
#define FBNIC_RXB_DWRR_RDE_WEIGHT1 0x08030 /* 0x200c0 */
#define FBNIC_RXB_DWRR_RDE_WEIGHT1_QUANTUM4 CSR_GENMASK(7, 0)
#define FBNIC_RXB_DWRR_BMC_WEIGHT 0x08031 /* 0x200c4 */
#define FBNIC_RXB_CLDR_PRIO_CFG(n) (0x8034 + (n)) /* 0x200d0 + 4*n */
#define FBNIC_RXB_CLDR_PRIO_CFG_CNT 16
#define FBNIC_RXB_ENDIAN_FCS 0x08044 /* 0x20110 */
enum {
/* Unused */
/* Unused */
FBNIC_RXB_DEQUEUE_BMC = 2,
FBNIC_RXB_DEQUEUE_HOST = 3,
FBNIC_RXB_DEQUEUE_INDICES = 4
};
#define FBNIC_RXB_PBUF_CREDIT(n) (0x08047 + (n)) /* 0x2011C + 4*n */
#define FBNIC_RXB_PBUF_CREDIT_CNT 8
#define FBNIC_RXB_PBUF_CREDIT_MASK CSR_GENMASK(13, 0)
#define FBNIC_RXB_INTF_CREDIT 0x0804f /* 0x2013C */
#define FBNIC_RXB_INTF_CREDIT_MASK0 CSR_GENMASK(3, 0)
#define FBNIC_RXB_INTF_CREDIT_MASK1 CSR_GENMASK(7, 4)
#define FBNIC_RXB_INTF_CREDIT_MASK2 CSR_GENMASK(11, 8)
#define FBNIC_RXB_INTF_CREDIT_MASK3 CSR_GENMASK(15, 12)
#define FBNIC_RXB_PAUSE_EVENT_CNT(n) (0x08053 + (n)) /* 0x2014c + 4*n */
#define FBNIC_RXB_DROP_FRMS_STS(n) (0x08057 + (n)) /* 0x2015c + 4*n */
#define FBNIC_RXB_DROP_BYTES_STS_L(n) \
(0x08080 + 2 * (n)) /* 0x20200 + 8*n */
#define FBNIC_RXB_DROP_BYTES_STS_H(n) \
(0x08081 + 2 * (n)) /* 0x20204 + 8*n */
#define FBNIC_RXB_TRUN_FRMS_STS(n) (0x08091 + (n)) /* 0x20244 + 4*n */
#define FBNIC_RXB_TRUN_BYTES_STS_L(n) \
(0x080c0 + 2 * (n)) /* 0x20300 + 8*n */
#define FBNIC_RXB_TRUN_BYTES_STS_H(n) \
(0x080c1 + 2 * (n)) /* 0x20304 + 8*n */
#define FBNIC_RXB_TRANS_PAUSE_STS(n) (0x080d1 + (n)) /* 0x20344 + 4*n */
#define FBNIC_RXB_TRANS_DROP_STS(n) (0x080d9 + (n)) /* 0x20364 + 4*n */
#define FBNIC_RXB_TRANS_ECN_STS(n) (0x080e1 + (n)) /* 0x20384 + 4*n */
enum {
FBNIC_RXB_ENQUEUE_NET = 0,
FBNIC_RXB_ENQUEUE_BMC = 1,
/* Unused */
/* Unused */
FBNIC_RXB_ENQUEUE_INDICES = 4
};
#define FBNIC_RXB_DRBO_FRM_CNT_SRC(n) (0x080f9 + (n)) /* 0x203e4 + 4*n */
#define FBNIC_RXB_DRBO_BYTE_CNT_SRC_L(n) \
(0x080fd + (n)) /* 0x203f4 + 4*n */
#define FBNIC_RXB_DRBO_BYTE_CNT_SRC_H(n) \
(0x08101 + (n)) /* 0x20404 + 4*n */
#define FBNIC_RXB_INTF_FRM_CNT_DST(n) (0x08105 + (n)) /* 0x20414 + 4*n */
#define FBNIC_RXB_INTF_BYTE_CNT_DST_L(n) \
(0x08109 + (n)) /* 0x20424 + 4*n */
#define FBNIC_RXB_INTF_BYTE_CNT_DST_H(n) \
(0x0810d + (n)) /* 0x20434 + 4*n */
#define FBNIC_RXB_PBUF_FRM_CNT_DST(n) (0x08111 + (n)) /* 0x20444 + 4*n */
#define FBNIC_RXB_PBUF_BYTE_CNT_DST_L(n) \
(0x08115 + (n)) /* 0x20454 + 4*n */
#define FBNIC_RXB_PBUF_BYTE_CNT_DST_H(n) \
(0x08119 + (n)) /* 0x20464 + 4*n */
#define FBNIC_RXB_PBUF_FIFO_LEVEL(n) (0x0811d + (n)) /* 0x20474 + 4*n */
#define FBNIC_RXB_INTEGRITY_ERR(n) (0x0812f + (n)) /* 0x204bc + 4*n */
#define FBNIC_RXB_MAC_ERR(n) (0x08133 + (n)) /* 0x204cc + 4*n */
#define FBNIC_RXB_PARSER_ERR(n) (0x08137 + (n)) /* 0x204dc + 4*n */
#define FBNIC_RXB_FRM_ERR(n) (0x0813b + (n)) /* 0x204ec + 4*n */
#define FBNIC_RXB_DWRR_RDE_WEIGHT0_EXT 0x08143 /* 0x2050c */
#define FBNIC_RXB_DWRR_RDE_WEIGHT1_EXT 0x08144 /* 0x20510 */
#define FBNIC_CSR_END_RXB 0x081b1 /* CSR section delimiter */
/* Rx Parser and Classifier Registers */
#define FBNIC_CSR_START_RPC 0x08400 /* CSR section delimiter */
#define FBNIC_RPC_RMI_CONFIG 0x08400 /* 0x21000 */
#define FBNIC_RPC_RMI_CONFIG_OH_BYTES CSR_GENMASK(4, 0)
#define FBNIC_RPC_RMI_CONFIG_FCS_PRESENT CSR_BIT(8)
#define FBNIC_RPC_RMI_CONFIG_ENABLE CSR_BIT(12)
#define FBNIC_RPC_RMI_CONFIG_MTU CSR_GENMASK(31, 16)
#define FBNIC_CSR_END_RPC 0x0856b /* CSR section delimiter */
/* Fab Registers */
#define FBNIC_CSR_START_FAB 0x0C000 /* CSR section delimiter */
#define FBNIC_FAB_AXI4_AR_SPACER_2_CFG 0x0C005 /* 0x30014 */
#define FBNIC_FAB_AXI4_AR_SPACER_MASK CSR_BIT(16)
#define FBNIC_FAB_AXI4_AR_SPACER_THREADSHOLD CSR_GENMASK(15, 0)
#define FBNIC_CSR_END_FAB 0x0C020 /* CSR section delimiter */
/* Master Registers */
#define FBNIC_CSR_START_MASTER 0x0C400 /* CSR section delimiter */
#define FBNIC_MASTER_SPARE_0 0x0C41B /* 0x3106c */
#define FBNIC_CSR_END_MASTER 0x0C452 /* CSR section delimiter */
/* PUL User Registers */
#define FBNIC_CSR_START_PUL_USER 0x31000 /* CSR section delimiter */
#define FBNIC_PUL_OB_TLP_HDR_AW_CFG 0x3103d /* 0xc40f4 */
#define FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME CSR_BIT(18)
#define FBNIC_PUL_OB_TLP_HDR_AR_CFG 0x3103e /* 0xc40f8 */
#define FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME CSR_BIT(18)
#define FBNIC_CSR_END_PUL_USER 0x31080 /* CSR section delimiter */
#define FBNIC_MAX_QUEUES 128
/* BAR 4 CSRs */
/* The IPC mailbox consists of 32 mailboxes, with each mailbox consisting
* of 32 4 byte registers. We will use 2 registers per descriptor so the
* length of the mailbox is reduced to 16.
*
* Currently we use an offset of 0x6000 on BAR4 for the mailbox so we just
* have to do the math and determine the offset based on the mailbox
* direction and index inside that mailbox.
*/
#define FBNIC_IPC_MBX_DESC_LEN 16
#define FBNIC_IPC_MBX(mbx_idx, desc_idx) \
((((mbx_idx) * FBNIC_IPC_MBX_DESC_LEN + (desc_idx)) * 2) + 0x6000)
/* Use first register in mailbox to flush writes */
#define FBNIC_FW_ZERO_REG FBNIC_IPC_MBX(0, 0)
enum {
FBNIC_IPC_MBX_RX_IDX,
FBNIC_IPC_MBX_TX_IDX,
FBNIC_IPC_MBX_INDICES,
};
#define FBNIC_IPC_MBX_DESC_LEN_MASK DESC_GENMASK(63, 48)
#define FBNIC_IPC_MBX_DESC_EOM DESC_BIT(46)
#define FBNIC_IPC_MBX_DESC_ADDR_MASK DESC_GENMASK(45, 3)
#define FBNIC_IPC_MBX_DESC_FW_CMPL DESC_BIT(1)
#define FBNIC_IPC_MBX_DESC_HOST_CMPL DESC_BIT(0)
#endif /* _FBNIC_CSR_H_ */
|
