path: root/drivers/net/ethernet/meta/fbnic/fbnic_csr.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) Meta Platforms, Inc. and affiliates. */

#ifndef _FBNIC_CSR_H_
#define _FBNIC_CSR_H_

#include <linux/bitops.h>

#define CSR_BIT(nr)		(1u << (nr))
#define CSR_GENMASK(h, l)	GENMASK(h, l)

#define DESC_BIT(nr)		BIT_ULL(nr)
#define DESC_GENMASK(h, l)	GENMASK_ULL(h, l)

/* Defines the minimum firmware version required by the driver */
#define MIN_FW_MAJOR_VERSION    0
#define MIN_FW_MINOR_VERSION    10
#define MIN_FW_BUILD_VERSION    6
#define MIN_FW_VERSION_CODE     (MIN_FW_MAJOR_VERSION * (1u << 24) + \
				 MIN_FW_MINOR_VERSION * (1u << 16) + \
				 MIN_FW_BUILD_VERSION)

#define PCI_DEVICE_ID_META_FBNIC_ASIC		0x0013

#define FBNIC_CLOCK_FREQ	(600 * (1000 * 1000))

/* Rx Buffer Descriptor Format
 *
 * The layout of this can vary depending on the page size of the system.
 *
 * If the page size is 4K then the layout will simply consist of ID for
 * the 16 most significant bits, and the lower 46 are essentially the page
 * address with the lowest 12 bits being reserved 0 due to the fact that
 * a page will be aligned.
 *
 * If the page size is larger than 4K then the lower n bits of the ID and
 * page address will be reserved for the fragment ID. This fragment will
 * be 4K in size and will be used to index both the DMA address and the ID
 * by the same amount.
 */
#define FBNIC_BD_DESC_ADDR_MASK			DESC_GENMASK(45, 12)
#define FBNIC_BD_DESC_ID_MASK			DESC_GENMASK(63, 48)
#define FBNIC_BD_FRAG_SIZE \
	(FBNIC_BD_DESC_ADDR_MASK & ~(FBNIC_BD_DESC_ADDR_MASK - 1))
#define FBNIC_BD_FRAG_COUNT \
	(PAGE_SIZE / FBNIC_BD_FRAG_SIZE)
#define FBNIC_BD_FRAG_ADDR_MASK \
	(FBNIC_BD_DESC_ADDR_MASK & \
	 ~(FBNIC_BD_DESC_ADDR_MASK * FBNIC_BD_FRAG_COUNT))
#define FBNIC_BD_FRAG_ID_MASK \
	(FBNIC_BD_DESC_ID_MASK & \
	 ~(FBNIC_BD_DESC_ID_MASK * FBNIC_BD_FRAG_COUNT))
#define FBNIC_BD_PAGE_ADDR_MASK \
	(FBNIC_BD_DESC_ADDR_MASK & ~FBNIC_BD_FRAG_ADDR_MASK)
#define FBNIC_BD_PAGE_ID_MASK \
	(FBNIC_BD_DESC_ID_MASK & ~FBNIC_BD_FRAG_ID_MASK)

/* Register Definitions
 *
 * The registers are laid as indexes into an le32 array. As such the actual
 * address is 4 times the index value. Below each register is defined as 3
 * fields, name, index, and Address.
 *
 *      Name				Index		Address
 *************************************************************************/
/* Interrupt Registers */
#define FBNIC_CSR_START_INTR		0x00000	/* CSR section delimiter */
#define FBNIC_INTR_STATUS(n)		(0x00000 + (n))	/* 0x00000 + 4*n */
#define FBNIC_INTR_STATUS_CNT			8
#define FBNIC_INTR_MASK(n)		(0x00008 + (n)) /* 0x00020 + 4*n */
#define FBNIC_INTR_MASK_CNT			8
#define FBNIC_INTR_SET(n)		(0x00010 + (n))	/* 0x00040 + 4*n */
#define FBNIC_INTR_SET_CNT			8
#define FBNIC_INTR_CLEAR(n)		(0x00018 + (n))	/* 0x00060 + 4*n */
#define FBNIC_INTR_CLEAR_CNT			8
#define FBNIC_INTR_SW_STATUS(n)		(0x00020 + (n)) /* 0x00080 + 4*n */
#define FBNIC_INTR_SW_STATUS_CNT		8
#define FBNIC_INTR_SW_AC_MODE(n)	(0x00028 + (n)) /* 0x000a0 + 4*n */
#define FBNIC_INTR_SW_AC_MODE_CNT		8
#define FBNIC_INTR_MASK_SET(n)		(0x00030 + (n)) /* 0x000c0 + 4*n */
#define FBNIC_INTR_MASK_SET_CNT			8
#define FBNIC_INTR_MASK_CLEAR(n)	(0x00038 + (n)) /* 0x000e0 + 4*n */
#define FBNIC_INTR_MASK_CLEAR_CNT		8
#define FBNIC_MAX_MSIX_VECS		256U
#define FBNIC_INTR_MSIX_CTRL(n)		(0x00040 + (n)) /* 0x00100 + 4*n */
#define FBNIC_INTR_MSIX_CTRL_VECTOR_MASK	CSR_GENMASK(7, 0)
#define FBNIC_INTR_MSIX_CTRL_ENABLE		CSR_BIT(31)

#define FBNIC_CSR_END_INTR		0x0005f	/* CSR section delimiter */

/* Interrupt MSIX Registers */
#define FBNIC_CSR_START_INTR_CQ		0x00400	/* CSR section delimiter */
#define FBNIC_INTR_CQ_REARM(n) \
				(0x00400 + 4 * (n))	/* 0x01000 + 16*n */
#define FBNIC_INTR_CQ_REARM_CNT			256
#define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT		CSR_GENMASK(13, 0)
#define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT_UPD_EN	CSR_BIT(14)
#define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT		CSR_GENMASK(28, 15)
#define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT_UPD_EN	CSR_BIT(29)
#define FBNIC_INTR_CQ_REARM_INTR_RELOAD		CSR_BIT(30)
#define FBNIC_INTR_CQ_REARM_INTR_UNMASK		CSR_BIT(31)

#define FBNIC_INTR_RCQ_TIMEOUT(n) \
				(0x00401 + 4 * (n))	/* 0x01004 + 16*n */
#define FBNIC_INTR_RCQ_TIMEOUT_CNT		256
#define FBNIC_INTR_TCQ_TIMEOUT(n) \
				(0x00402 + 4 * (n))	/* 0x01008 + 16*n */
#define FBNIC_INTR_TCQ_TIMEOUT_CNT		256
#define FBNIC_CSR_END_INTR_CQ		0x007fe	/* CSR section delimiter */

/* Global QM Tx registers */
#define FBNIC_CSR_START_QM_TX		0x00800	/* CSR section delimiter */
#define FBNIC_QM_TWQ_IDLE(n)		(0x00800 + (n)) /* 0x02000 + 4*n */
#define FBNIC_QM_TWQ_IDLE_CNT			8
#define FBNIC_QM_TWQ_DEFAULT_META_L	0x00818		/* 0x02060 */
#define FBNIC_QM_TWQ_DEFAULT_META_H	0x00819		/* 0x02064 */

#define FBNIC_QM_TQS_CTL0		0x0081b		/* 0x0206c */
#define FBNIC_QM_TQS_CTL0_LSO_TS_MASK	CSR_BIT(0)
enum {
	FBNIC_QM_TQS_CTL0_LSO_TS_FIRST	= 0,
	FBNIC_QM_TQS_CTL0_LSO_TS_LAST	= 1,
};

#define FBNIC_QM_TQS_CTL0_PREFETCH_THRESH	CSR_GENMASK(7, 1)
enum {
	FBNIC_QM_TQS_CTL0_PREFETCH_THRESH_MIN	= 16,
};

#define FBNIC_QM_TQS_CTL1		0x0081c		/* 0x02070 */
#define FBNIC_QM_TQS_CTL1_MC_MAX_CREDITS	CSR_GENMASK(7, 0)
#define FBNIC_QM_TQS_CTL1_BULK_MAX_CREDITS	CSR_GENMASK(15, 8)
#define FBNIC_QM_TQS_MTU_CTL0		0x0081d		/* 0x02074 */
#define FBNIC_QM_TQS_MTU_CTL1		0x0081e		/* 0x02078 */
#define FBNIC_QM_TQS_MTU_CTL1_BULK		CSR_GENMASK(13, 0)
#define FBNIC_QM_TCQ_IDLE(n)		(0x00821 + (n)) /* 0x02084 + 4*n */
#define FBNIC_QM_TCQ_IDLE_CNT			4
#define FBNIC_QM_TCQ_CTL0		0x0082d		/* 0x020b4 */
#define FBNIC_QM_TCQ_CTL0_COAL_WAIT		CSR_GENMASK(15, 0)
#define FBNIC_QM_TCQ_CTL0_TICK_CYCLES		CSR_GENMASK(26, 16)
#define FBNIC_QM_TQS_IDLE(n)		(0x00830 + (n)) /* 0x020c0 + 4*n */
#define FBNIC_QM_TQS_IDLE_CNT			8
#define FBNIC_QM_TQS_EDT_TS_RANGE	0x00849		/* 0x2124 */
#define FBNIC_QM_TDE_IDLE(n)		(0x00853 + (n)) /* 0x0214c + 4*n */
#define FBNIC_QM_TDE_IDLE_CNT			8
#define FBNIC_QM_TNI_TDF_CTL		0x0086c		/* 0x021b0 */
#define FBNIC_QM_TNI_TDF_CTL_MRRS		CSR_GENMASK(1, 0)
#define FBNIC_QM_TNI_TDF_CTL_CLS		CSR_GENMASK(3, 2)
#define FBNIC_QM_TNI_TDF_CTL_MAX_OT		CSR_GENMASK(11, 4)
#define FBNIC_QM_TNI_TDF_CTL_MAX_OB		CSR_GENMASK(23, 12)
#define FBNIC_QM_TNI_TDE_CTL		0x0086d		/* 0x021b4 */
#define FBNIC_QM_TNI_TDE_CTL_MRRS		CSR_GENMASK(1, 0)
#define FBNIC_QM_TNI_TDE_CTL_CLS		CSR_GENMASK(3, 2)
#define FBNIC_QM_TNI_TDE_CTL_MAX_OT		CSR_GENMASK(11, 4)
#define FBNIC_QM_TNI_TDE_CTL_MAX_OB		CSR_GENMASK(24, 12)
#define FBNIC_QM_TNI_TDE_CTL_MRRS_1K		CSR_BIT(25)
#define FBNIC_QM_TNI_TCM_CTL		0x0086e		/* 0x021b8 */
#define FBNIC_QM_TNI_TCM_CTL_MPS		CSR_GENMASK(1, 0)
#define FBNIC_QM_TNI_TCM_CTL_CLS		CSR_GENMASK(3, 2)
#define FBNIC_QM_TNI_TCM_CTL_MAX_OT		CSR_GENMASK(11, 4)
#define FBNIC_QM_TNI_TCM_CTL_MAX_OB		CSR_GENMASK(23, 12)
#define FBNIC_CSR_END_QM_TX		0x00873	/* CSR section delimiter */

/* Global QM Rx registers */
#define FBNIC_CSR_START_QM_RX		0x00c00	/* CSR section delimiter */
#define FBNIC_QM_RCQ_IDLE(n)		(0x00c00 + (n)) /* 0x03000 + 4*n */
#define FBNIC_QM_RCQ_IDLE_CNT			4
#define FBNIC_QM_RCQ_CTL0		0x00c0c		/* 0x03030 */
#define FBNIC_QM_RCQ_CTL0_COAL_WAIT		CSR_GENMASK(15, 0)
#define FBNIC_QM_RCQ_CTL0_TICK_CYCLES		CSR_GENMASK(26, 16)
#define FBNIC_QM_HPQ_IDLE(n)		(0x00c0f + (n)) /* 0x0303c + 4*n */
#define FBNIC_QM_HPQ_IDLE_CNT			4
#define FBNIC_QM_PPQ_IDLE(n)		(0x00c13 + (n)) /* 0x0304c + 4*n */
#define FBNIC_QM_PPQ_IDLE_CNT			4
#define FBNIC_QM_RNI_RBP_CTL		0x00c2d		/* 0x030b4 */
#define FBNIC_QM_RNI_RBP_CTL_MRRS		CSR_GENMASK(1, 0)
#define FBNIC_QM_RNI_RBP_CTL_CLS		CSR_GENMASK(3, 2)
#define FBNIC_QM_RNI_RBP_CTL_MAX_OT		CSR_GENMASK(11, 4)
#define FBNIC_QM_RNI_RBP_CTL_MAX_OB		CSR_GENMASK(23, 12)
#define FBNIC_QM_RNI_RDE_CTL		0x00c2e		/* 0x030b8 */
#define FBNIC_QM_RNI_RDE_CTL_MPS		CSR_GENMASK(1, 0)
#define FBNIC_QM_RNI_RDE_CTL_CLS		CSR_GENMASK(3, 2)
#define FBNIC_QM_RNI_RDE_CTL_MAX_OT		CSR_GENMASK(11, 4)
#define FBNIC_QM_RNI_RDE_CTL_MAX_OB		CSR_GENMASK(23, 12)
#define FBNIC_QM_RNI_RCM_CTL		0x00c2f		/* 0x030bc */
#define FBNIC_QM_RNI_RCM_CTL_MPS		CSR_GENMASK(1, 0)
#define FBNIC_QM_RNI_RCM_CTL_CLS		CSR_GENMASK(3, 2)
#define FBNIC_QM_RNI_RCM_CTL_MAX_OT		CSR_GENMASK(11, 4)
#define FBNIC_QM_RNI_RCM_CTL_MAX_OB		CSR_GENMASK(23, 12)
#define FBNIC_CSR_END_QM_RX		0x00c34	/* CSR section delimiter */

/* TCE registers */
#define FBNIC_CSR_START_TCE		0x04000	/* CSR section delimiter */
#define FBNIC_TCE_REG_BASE		0x04000		/* 0x10000 */

#define FBNIC_TCE_LSO_CTRL		0x04000		/* 0x10000 */
#define FBNIC_TCE_LSO_CTRL_TCPF_CLR_1ST		CSR_GENMASK(8, 0)
#define FBNIC_TCE_LSO_CTRL_TCPF_CLR_MID		CSR_GENMASK(17, 9)
#define FBNIC_TCE_LSO_CTRL_TCPF_CLR_END		CSR_GENMASK(26, 18)
#define FBNIC_TCE_LSO_CTRL_IPID_MODE_INC	CSR_BIT(27)

#define FBNIC_TCE_CSO_CTRL		0x04001		/* 0x10004 */
#define FBNIC_TCE_CSO_CTRL_TCP_ZERO_CSUM	CSR_BIT(0)

#define FBNIC_TCE_TXB_CTRL		0x04002		/* 0x10008 */
#define FBNIC_TCE_TXB_CTRL_LOAD			CSR_BIT(0)
#define FBNIC_TCE_TXB_CTRL_TCAM_ENABLE		CSR_BIT(1)
#define FBNIC_TCE_TXB_CTRL_DISABLE		CSR_BIT(2)

#define FBNIC_TCE_TXB_ENQ_WRR_CTRL	0x04003		/* 0x1000c */
#define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT0	CSR_GENMASK(7, 0)
#define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT1	CSR_GENMASK(15, 8)
#define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT2	CSR_GENMASK(23, 16)

#define FBNIC_TCE_TXB_TEI_Q0_CTRL	0x04004		/* 0x10010 */
#define FBNIC_TCE_TXB_TEI_Q1_CTRL	0x04005		/* 0x10014 */
#define FBNIC_TCE_TXB_MC_Q_CTRL		0x04006		/* 0x10018 */
#define FBNIC_TCE_TXB_RX_TEI_Q_CTRL	0x04007		/* 0x1001c */
#define FBNIC_TCE_TXB_RX_BMC_Q_CTRL	0x04008		/* 0x10020 */
#define FBNIC_TCE_TXB_Q_CTRL_START		CSR_GENMASK(10, 0)
#define FBNIC_TCE_TXB_Q_CTRL_SIZE		CSR_GENMASK(22, 11)

#define FBNIC_TCE_TXB_TEI_DWRR_CTRL	0x04009		/* 0x10024 */
#define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM0	CSR_GENMASK(7, 0)
#define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM1	CSR_GENMASK(15, 8)
#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL	0x0400a		/* 0x10028 */
#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM0	CSR_GENMASK(7, 0)
#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM1	CSR_GENMASK(15, 8)
#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM2	CSR_GENMASK(23, 16)

#define FBNIC_TCE_TXB_CLDR_CFG		0x0400b		/* 0x1002c */
#define FBNIC_TCE_TXB_CLDR_CFG_NUM_SLOT		CSR_GENMASK(5, 0)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG(n)	(0x0400c + (n))	/* 0x10030 + 4*n */
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_CNT		16
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_0	CSR_GENMASK(1, 0)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_1	CSR_GENMASK(3, 2)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_2	CSR_GENMASK(5, 4)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_3	CSR_GENMASK(7, 6)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_0	CSR_GENMASK(9, 8)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_1	CSR_GENMASK(11, 10)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_2	CSR_GENMASK(13, 12)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_3	CSR_GENMASK(15, 14)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_0	CSR_GENMASK(17, 16)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_1	CSR_GENMASK(19, 18)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_2	CSR_GENMASK(21, 20)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_3	CSR_GENMASK(23, 22)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_0	CSR_GENMASK(25, 24)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_1	CSR_GENMASK(27, 26)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_2	CSR_GENMASK(29, 28)
#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_3	CSR_GENMASK(31, 30)

#define FBNIC_TCE_BMC_MAX_PKTSZ		0x0403a		/* 0x100e8 */
#define FBNIC_TCE_BMC_MAX_PKTSZ_TX		CSR_GENMASK(13, 0)
#define FBNIC_TCE_BMC_MAX_PKTSZ_RX		CSR_GENMASK(27, 14)
#define FBNIC_TCE_MC_MAX_PKTSZ		0x0403b		/* 0x100ec */
#define FBNIC_TCE_MC_MAX_PKTSZ_TMI		CSR_GENMASK(13, 0)

#define FBNIC_TCE_SOP_PROT_CTRL		0x0403c		/* 0x100f0 */
#define FBNIC_TCE_SOP_PROT_CTRL_TBI		CSR_GENMASK(7, 0)
#define FBNIC_TCE_SOP_PROT_CTRL_TTI_FRM		CSR_GENMASK(14, 8)
#define FBNIC_TCE_SOP_PROT_CTRL_TTI_CM		CSR_GENMASK(18, 15)

#define FBNIC_TCE_DROP_CTRL		0x0403d		/* 0x100f4 */
#define FBNIC_TCE_DROP_CTRL_TTI_CM_DROP_EN	CSR_BIT(0)
#define FBNIC_TCE_DROP_CTRL_TTI_FRM_DROP_EN	CSR_BIT(1)
#define FBNIC_TCE_DROP_CTRL_TTI_TBI_DROP_EN	CSR_BIT(2)

#define FBNIC_TCE_TXB_TX_BMC_Q_CTRL	0x0404B		/* 0x1012c */
#define FBNIC_TCE_TXB_BMC_DWRR_CTRL	0x0404C		/* 0x10130 */
#define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM0	CSR_GENMASK(7, 0)
#define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM1	CSR_GENMASK(15, 8)
#define FBNIC_TCE_TXB_TEI_DWRR_CTRL_EXT	0x0404D		/* 0x10134 */
#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_EXT \
					0x0404E		/* 0x10138 */
#define FBNIC_TCE_TXB_BMC_DWRR_CTRL_EXT	0x0404F		/* 0x1013c */
#define FBNIC_CSR_END_TCE		0x04050	/* CSR section delimiter */

/* TMI registers */
#define FBNIC_CSR_START_TMI		0x04400	/* CSR section delimiter */
#define FBNIC_TMI_SOP_PROT_CTRL		0x04400		/* 0x11000 */
#define FBNIC_TMI_DROP_CTRL		0x04401		/* 0x11004 */
#define FBNIC_TMI_DROP_CTRL_EN			CSR_BIT(0)
#define FBNIC_CSR_END_TMI		0x0443f	/* CSR section delimiter */
/* Rx Buffer Registers */
#define FBNIC_CSR_START_RXB		0x08000	/* CSR section delimiter */
enum {
	FBNIC_RXB_FIFO_MC		= 0,
	/* Unused */
	/* Unused */
	FBNIC_RXB_FIFO_NET_TO_BMC	= 3,
	FBNIC_RXB_FIFO_HOST		= 4,
	/* Unused */
	FBNIC_RXB_FIFO_BMC_TO_HOST	= 6,
	/* Unused */
	FBNIC_RXB_FIFO_INDICES		= 8
};

#define FBNIC_RXB_CT_SIZE(n)		(0x08000 + (n))	/* 0x20000 + 4*n */
#define FBNIC_RXB_CT_SIZE_CNT			8
#define FBNIC_RXB_CT_SIZE_HEADER		CSR_GENMASK(5, 0)
#define FBNIC_RXB_CT_SIZE_PAYLOAD		CSR_GENMASK(11, 6)
#define FBNIC_RXB_CT_SIZE_ENABLE		CSR_BIT(12)
#define FBNIC_RXB_PAUSE_DROP_CTRL	0x08008		/* 0x20020 */
#define FBNIC_RXB_PAUSE_DROP_CTRL_DROP_ENABLE	CSR_GENMASK(7, 0)
#define FBNIC_RXB_PAUSE_DROP_CTRL_PAUSE_ENABLE	CSR_GENMASK(15, 8)
#define FBNIC_RXB_PAUSE_DROP_CTRL_ECN_ENABLE	CSR_GENMASK(23, 16)
#define FBNIC_RXB_PAUSE_DROP_CTRL_PS_ENABLE	CSR_GENMASK(27, 24)
#define FBNIC_RXB_PAUSE_THLD(n)		(0x08009 + (n)) /* 0x20024 + 4*n */
#define FBNIC_RXB_PAUSE_THLD_CNT		8
#define FBNIC_RXB_PAUSE_THLD_ON			CSR_GENMASK(12, 0)
#define FBNIC_RXB_PAUSE_THLD_OFF		CSR_GENMASK(25, 13)
#define FBNIC_RXB_DROP_THLD(n)		(0x08011 + (n)) /* 0x20044 + 4*n */
#define FBNIC_RXB_DROP_THLD_CNT			8
#define FBNIC_RXB_DROP_THLD_ON			CSR_GENMASK(12, 0)
#define FBNIC_RXB_DROP_THLD_OFF			CSR_GENMASK(25, 13)
#define FBNIC_RXB_ECN_THLD(n)		(0x0801e + (n)) /* 0x20078 + 4*n */
#define FBNIC_RXB_ECN_THLD_CNT			8
#define FBNIC_RXB_ECN_THLD_ON			CSR_GENMASK(12, 0)
#define FBNIC_RXB_ECN_THLD_OFF			CSR_GENMASK(25, 13)
#define FBNIC_RXB_PBUF_CFG(n)		(0x08027 + (n))	/* 0x2009c + 4*n */
#define FBNIC_RXB_PBUF_CFG_CNT			8
#define FBNIC_RXB_PBUF_BASE_ADDR		CSR_GENMASK(12, 0)
#define FBNIC_RXB_PBUF_SIZE			CSR_GENMASK(21, 13)
#define FBNIC_RXB_DWRR_RDE_WEIGHT0	0x0802f		/* 0x200bc */
#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM0	CSR_GENMASK(7, 0)
#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM1	CSR_GENMASK(15, 8)
#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM2	CSR_GENMASK(23, 16)
#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM3	CSR_GENMASK(31, 24)
#define FBNIC_RXB_DWRR_RDE_WEIGHT1	0x08030		/* 0x200c0 */
#define FBNIC_RXB_DWRR_RDE_WEIGHT1_QUANTUM4	CSR_GENMASK(7, 0)
#define FBNIC_RXB_DWRR_BMC_WEIGHT	0x08031		/* 0x200c4 */
#define FBNIC_RXB_CLDR_PRIO_CFG(n)	(0x8034 + (n))	/* 0x200d0 + 4*n */
#define FBNIC_RXB_CLDR_PRIO_CFG_CNT		16
#define FBNIC_RXB_ENDIAN_FCS		0x08044		/* 0x20110 */
enum {
	/* Unused */
	/* Unused */
	FBNIC_RXB_DEQUEUE_BMC		= 2,
	FBNIC_RXB_DEQUEUE_HOST		= 3,
	FBNIC_RXB_DEQUEUE_INDICES	= 4
};

#define FBNIC_RXB_PBUF_CREDIT(n)	(0x08047 + (n))	/* 0x2011C + 4*n */
#define FBNIC_RXB_PBUF_CREDIT_CNT		8
#define FBNIC_RXB_PBUF_CREDIT_MASK		CSR_GENMASK(13, 0)
#define FBNIC_RXB_INTF_CREDIT		0x0804f		/* 0x2013C */
#define FBNIC_RXB_INTF_CREDIT_MASK0		CSR_GENMASK(3, 0)
#define FBNIC_RXB_INTF_CREDIT_MASK1		CSR_GENMASK(7, 4)
#define FBNIC_RXB_INTF_CREDIT_MASK2		CSR_GENMASK(11, 8)
#define FBNIC_RXB_INTF_CREDIT_MASK3		CSR_GENMASK(15, 12)

#define FBNIC_RXB_PAUSE_EVENT_CNT(n)	(0x08053 + (n))	/* 0x2014c + 4*n */
#define FBNIC_RXB_DROP_FRMS_STS(n)	(0x08057 + (n))	/* 0x2015c + 4*n */
#define FBNIC_RXB_DROP_BYTES_STS_L(n) \
				(0x08080 + 2 * (n))	/* 0x20200 + 8*n */
#define FBNIC_RXB_DROP_BYTES_STS_H(n) \
				(0x08081 + 2 * (n))	/* 0x20204 + 8*n */
#define FBNIC_RXB_TRUN_FRMS_STS(n)	(0x08091 + (n))	/* 0x20244 + 4*n */
#define FBNIC_RXB_TRUN_BYTES_STS_L(n) \
				(0x080c0 + 2 * (n))	/* 0x20300 + 8*n */
#define FBNIC_RXB_TRUN_BYTES_STS_H(n) \
				(0x080c1 + 2 * (n))	/* 0x20304 + 8*n */
#define FBNIC_RXB_TRANS_PAUSE_STS(n)	(0x080d1 + (n))	/* 0x20344 + 4*n */
#define FBNIC_RXB_TRANS_DROP_STS(n)	(0x080d9 + (n))	/* 0x20364 + 4*n */
#define FBNIC_RXB_TRANS_ECN_STS(n)	(0x080e1 + (n))	/* 0x20384 + 4*n */
enum {
	FBNIC_RXB_ENQUEUE_NET		= 0,
	FBNIC_RXB_ENQUEUE_BMC		= 1,
	/* Unused */
	/* Unused */
	FBNIC_RXB_ENQUEUE_INDICES	= 4
};

#define FBNIC_RXB_DRBO_FRM_CNT_SRC(n)	(0x080f9 + (n))	/* 0x203e4 + 4*n */
#define FBNIC_RXB_DRBO_BYTE_CNT_SRC_L(n) \
					(0x080fd + (n))	/* 0x203f4 + 4*n */
#define FBNIC_RXB_DRBO_BYTE_CNT_SRC_H(n) \
					(0x08101 + (n))	/* 0x20404 + 4*n */
#define FBNIC_RXB_INTF_FRM_CNT_DST(n)	(0x08105 + (n))	/* 0x20414 + 4*n */
#define FBNIC_RXB_INTF_BYTE_CNT_DST_L(n) \
					(0x08109 + (n))	/* 0x20424 + 4*n */
#define FBNIC_RXB_INTF_BYTE_CNT_DST_H(n) \
					(0x0810d + (n))	/* 0x20434 + 4*n */
#define FBNIC_RXB_PBUF_FRM_CNT_DST(n)	(0x08111 + (n))	/* 0x20444 + 4*n */
#define FBNIC_RXB_PBUF_BYTE_CNT_DST_L(n) \
					(0x08115 + (n))	/* 0x20454 + 4*n */
#define FBNIC_RXB_PBUF_BYTE_CNT_DST_H(n) \
					(0x08119 + (n))	/* 0x20464 + 4*n */

#define FBNIC_RXB_PBUF_FIFO_LEVEL(n)	(0x0811d + (n)) /* 0x20474 + 4*n */

#define FBNIC_RXB_INTEGRITY_ERR(n)	(0x0812f + (n))	/* 0x204bc + 4*n */
#define FBNIC_RXB_MAC_ERR(n)		(0x08133 + (n))	/* 0x204cc + 4*n */
#define FBNIC_RXB_PARSER_ERR(n)		(0x08137 + (n))	/* 0x204dc + 4*n */
#define FBNIC_RXB_FRM_ERR(n)		(0x0813b + (n))	/* 0x204ec + 4*n */

#define FBNIC_RXB_DWRR_RDE_WEIGHT0_EXT	0x08143		/* 0x2050c */
#define FBNIC_RXB_DWRR_RDE_WEIGHT1_EXT	0x08144		/* 0x20510 */
#define FBNIC_CSR_END_RXB		0x081b1	/* CSR section delimiter */

/* Rx Parser and Classifier Registers */
#define FBNIC_CSR_START_RPC		0x08400	/* CSR section delimiter */
#define FBNIC_RPC_RMI_CONFIG		0x08400		/* 0x21000 */
#define FBNIC_RPC_RMI_CONFIG_OH_BYTES		CSR_GENMASK(4, 0)
#define FBNIC_RPC_RMI_CONFIG_FCS_PRESENT	CSR_BIT(8)
#define FBNIC_RPC_RMI_CONFIG_ENABLE		CSR_BIT(12)
#define FBNIC_RPC_RMI_CONFIG_MTU		CSR_GENMASK(31, 16)
#define FBNIC_CSR_END_RPC		0x0856b	/* CSR section delimiter */

/* Fab Registers */
#define FBNIC_CSR_START_FAB		0x0C000 /* CSR section delimiter */
#define FBNIC_FAB_AXI4_AR_SPACER_2_CFG		0x0C005		/* 0x30014 */
#define FBNIC_FAB_AXI4_AR_SPACER_MASK		CSR_BIT(16)
#define FBNIC_FAB_AXI4_AR_SPACER_THREADSHOLD	CSR_GENMASK(15, 0)
#define FBNIC_CSR_END_FAB		0x0C020	    /* CSR section delimiter */

/* Master Registers */
#define FBNIC_CSR_START_MASTER		0x0C400	/* CSR section delimiter */
#define FBNIC_MASTER_SPARE_0		0x0C41B		/* 0x3106c */
#define FBNIC_CSR_END_MASTER		0x0C452	/* CSR section delimiter */

/* PUL User Registers */
#define FBNIC_CSR_START_PUL_USER	0x31000	/* CSR section delimiter */
#define FBNIC_PUL_OB_TLP_HDR_AW_CFG	0x3103d		/* 0xc40f4 */
#define FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME		CSR_BIT(18)
#define FBNIC_PUL_OB_TLP_HDR_AR_CFG	0x3103e		/* 0xc40f8 */
#define FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME		CSR_BIT(18)
#define FBNIC_CSR_END_PUL_USER	0x31080	/* CSR section delimiter */

/* Queue Registers
 *
 * The queue register offsets are specific for a given queue grouping. So to
 * find the actual register offset it is necessary to combine FBNIC_QUEUE(n)
 * with the register to get the actual register offset like so:
 *   FBNIC_QUEUE_TWQ0_CTL(n) == FBNIC_QUEUE(n) + FBNIC_QUEUE_TWQ0_CTL
 */
#define FBNIC_CSR_START_QUEUE		0x40000	/* CSR section delimiter */
#define FBNIC_QUEUE_STRIDE		0x400		/* 0x1000 */
#define FBNIC_QUEUE(n)\
	(0x40000 + FBNIC_QUEUE_STRIDE * (n))	/* 0x100000 + 4096*n */

#define FBNIC_QUEUE_TWQ0_CTL		0x000		/* 0x000 */
#define FBNIC_QUEUE_TWQ1_CTL		0x001		/* 0x004 */
#define FBNIC_QUEUE_TWQ_CTL_RESET		CSR_BIT(0)
#define FBNIC_QUEUE_TWQ_CTL_ENABLE		CSR_BIT(1)
#define FBNIC_QUEUE_TWQ0_TAIL		0x002		/* 0x008 */
#define FBNIC_QUEUE_TWQ1_TAIL		0x003		/* 0x00c */

#define FBNIC_QUEUE_TWQ0_SIZE		0x00a		/* 0x028 */
#define FBNIC_QUEUE_TWQ1_SIZE		0x00b		/* 0x02c */
#define FBNIC_QUEUE_TWQ_SIZE_MASK		CSR_GENMASK(3, 0)

#define FBNIC_QUEUE_TWQ0_BAL		0x020		/* 0x080 */
#define FBNIC_QUEUE_BAL_MASK			CSR_GENMASK(31, 7)
#define FBNIC_QUEUE_TWQ0_BAH		0x021		/* 0x084 */
#define FBNIC_QUEUE_TWQ1_BAL		0x022		/* 0x088 */
#define FBNIC_QUEUE_TWQ1_BAH		0x023		/* 0x08c */

/* Tx Completion Queue Registers */
#define FBNIC_QUEUE_TCQ_CTL		0x080		/* 0x200 */
#define FBNIC_QUEUE_TCQ_CTL_RESET		CSR_BIT(0)
#define FBNIC_QUEUE_TCQ_CTL_ENABLE		CSR_BIT(1)

#define FBNIC_QUEUE_TCQ_HEAD		0x081		/* 0x204 */

#define FBNIC_QUEUE_TCQ_SIZE		0x084		/* 0x210 */
#define FBNIC_QUEUE_TCQ_SIZE_MASK		CSR_GENMASK(3, 0)

#define FBNIC_QUEUE_TCQ_BAL		0x0a0		/* 0x280 */
#define FBNIC_QUEUE_TCQ_BAH		0x0a1		/* 0x284 */

/* Tx Interrupt Manager Registers */
#define FBNIC_QUEUE_TIM_CTL		0x0c0		/* 0x300 */
#define FBNIC_QUEUE_TIM_CTL_MSIX_MASK		CSR_GENMASK(7, 0)

#define FBNIC_QUEUE_TIM_THRESHOLD	0x0c1		/* 0x304 */
#define FBNIC_QUEUE_TIM_THRESHOLD_TWD_MASK	CSR_GENMASK(14, 0)

#define FBNIC_QUEUE_TIM_CLEAR		0x0c2		/* 0x308 */
#define FBNIC_QUEUE_TIM_CLEAR_MASK		CSR_BIT(0)
#define FBNIC_QUEUE_TIM_SET		0x0c3		/* 0x30c */
#define FBNIC_QUEUE_TIM_SET_MASK		CSR_BIT(0)
#define FBNIC_QUEUE_TIM_MASK		0x0c4		/* 0x310 */
#define FBNIC_QUEUE_TIM_MASK_MASK		CSR_BIT(0)

#define FBNIC_QUEUE_TIM_TIMER		0x0c5		/* 0x314 */

#define FBNIC_QUEUE_TIM_COUNTS		0x0c6		/* 0x318 */
#define FBNIC_QUEUE_TIM_COUNTS_CNT1_MASK	CSR_GENMASK(30, 16)
#define FBNIC_QUEUE_TIM_COUNTS_CNT0_MASK	CSR_GENMASK(14, 0)

/* Rx Completion Queue Registers */
#define FBNIC_QUEUE_RCQ_CTL		0x200		/* 0x800 */
#define FBNIC_QUEUE_RCQ_CTL_RESET		CSR_BIT(0)
#define FBNIC_QUEUE_RCQ_CTL_ENABLE		CSR_BIT(1)

#define FBNIC_QUEUE_RCQ_HEAD		0x201		/* 0x804 */

#define FBNIC_QUEUE_RCQ_SIZE		0x204		/* 0x810 */
#define FBNIC_QUEUE_RCQ_SIZE_MASK		CSR_GENMASK(3, 0)

#define FBNIC_QUEUE_RCQ_BAL		0x220		/* 0x880 */
#define FBNIC_QUEUE_RCQ_BAH		0x221		/* 0x884 */

/* Rx Buffer Descriptor Queue Registers */
#define FBNIC_QUEUE_BDQ_CTL		0x240		/* 0x900 */
#define FBNIC_QUEUE_BDQ_CTL_RESET		CSR_BIT(0)
#define FBNIC_QUEUE_BDQ_CTL_ENABLE		CSR_BIT(1)
#define FBNIC_QUEUE_BDQ_CTL_PPQ_ENABLE		CSR_BIT(30)

#define FBNIC_QUEUE_BDQ_HPQ_TAIL	0x241		/* 0x904 */
#define FBNIC_QUEUE_BDQ_PPQ_TAIL	0x242		/* 0x908 */

#define FBNIC_QUEUE_BDQ_HPQ_SIZE	0x247		/* 0x91c */
#define FBNIC_QUEUE_BDQ_PPQ_SIZE	0x248		/* 0x920 */
#define FBNIC_QUEUE_BDQ_SIZE_MASK		CSR_GENMASK(3, 0)

#define FBNIC_QUEUE_BDQ_HPQ_BAL		0x260		/* 0x980 */
#define FBNIC_QUEUE_BDQ_HPQ_BAH		0x261		/* 0x984 */
#define FBNIC_QUEUE_BDQ_PPQ_BAL		0x262		/* 0x988 */
#define FBNIC_QUEUE_BDQ_PPQ_BAH		0x263		/* 0x98c */

/* Rx DMA Engine Configuration */
#define FBNIC_QUEUE_RDE_CTL0		0x2a0		/* 0xa80 */
#define FBNIC_QUEUE_RDE_CTL0_EN_HDR_SPLIT	CSR_BIT(31)
#define FBNIC_QUEUE_RDE_CTL0_DROP_MODE_MASK	CSR_GENMASK(30, 29)
enum {
	FBNIC_QUEUE_RDE_CTL0_DROP_IMMEDIATE	= 0,
	FBNIC_QUEUE_RDE_CTL0_DROP_WAIT		= 1,
	FBNIC_QUEUE_RDE_CTL0_DROP_NEVER		= 2,
};

#define FBNIC_QUEUE_RDE_CTL0_MIN_HROOM_MASK	CSR_GENMASK(28, 20)
#define FBNIC_QUEUE_RDE_CTL0_MIN_TROOM_MASK	CSR_GENMASK(19, 11)

#define FBNIC_QUEUE_RDE_CTL1		0x2a1		/* 0xa84 */
#define FBNIC_QUEUE_RDE_CTL1_MAX_HDR_MASK	CSR_GENMASK(24, 12)
#define FBNIC_QUEUE_RDE_CTL1_PAYLD_OFF_MASK	CSR_GENMASK(11, 9)
#define FBNIC_QUEUE_RDE_CTL1_PAYLD_PG_CL_MASK	CSR_GENMASK(8, 6)
#define FBNIC_QUEUE_RDE_CTL1_PADLEN_MASK	CSR_GENMASK(5, 2)
#define FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_MASK	CSR_GENMASK(1, 0)
enum {
	FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_NONE	= 0,
	FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_ALL	= 1,
	FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_RSS	= 2,
};

/* Rx Interrupt Manager Registers */
#define FBNIC_QUEUE_RIM_CTL		0x2c0		/* 0xb00 */
#define FBNIC_QUEUE_RIM_CTL_MSIX_MASK		CSR_GENMASK(7, 0)

#define FBNIC_QUEUE_RIM_THRESHOLD	0x2c1		/* 0xb04 */
#define FBNIC_QUEUE_RIM_THRESHOLD_RCD_MASK	CSR_GENMASK(14, 0)

#define FBNIC_QUEUE_RIM_CLEAR		0x2c2		/* 0xb08 */
#define FBNIC_QUEUE_RIM_CLEAR_MASK		CSR_BIT(0)
#define FBNIC_QUEUE_RIM_SET		0x2c3		/* 0xb0c */
#define FBNIC_QUEUE_RIM_SET_MASK		CSR_BIT(0)
#define FBNIC_QUEUE_RIM_MASK		0x2c4		/* 0xb10 */
#define FBNIC_QUEUE_RIM_MASK_MASK		CSR_BIT(0)

#define FBNIC_QUEUE_RIM_COAL_STATUS	0x2c5		/* 0xb14 */
#define FBNIC_QUEUE_RIM_RCD_COUNT_MASK		CSR_GENMASK(30, 16)
#define FBNIC_QUEUE_RIM_TIMER_MASK		CSR_GENMASK(13, 0)
#define FBNIC_MAX_QUEUES		128
#define FBNIC_CSR_END_QUEUE	(0x40000 + 0x400 * FBNIC_MAX_QUEUES - 1)

/* BAR 4 CSRs */

/* The IPC mailbox consists of 32 mailboxes, with each mailbox consisting
 * of 32 4 byte registers. We will use 2 registers per descriptor so the
 * length of the mailbox is reduced to 16.
 *
 * Currently we use an offset of 0x6000 on BAR4 for the mailbox so we just
 * have to do the math and determine the offset based on the mailbox
 * direction and index inside that mailbox.
 */
#define FBNIC_IPC_MBX_DESC_LEN	16
#define FBNIC_IPC_MBX(mbx_idx, desc_idx)	\
	((((mbx_idx) * FBNIC_IPC_MBX_DESC_LEN + (desc_idx)) * 2) + 0x6000)

/* Use first register in mailbox to flush writes */
#define FBNIC_FW_ZERO_REG	FBNIC_IPC_MBX(0, 0)

enum {
	FBNIC_IPC_MBX_RX_IDX,
	FBNIC_IPC_MBX_TX_IDX,
	FBNIC_IPC_MBX_INDICES,
};

#define FBNIC_IPC_MBX_DESC_LEN_MASK	DESC_GENMASK(63, 48)
#define FBNIC_IPC_MBX_DESC_EOM		DESC_BIT(46)
#define FBNIC_IPC_MBX_DESC_ADDR_MASK	DESC_GENMASK(45, 3)
#define FBNIC_IPC_MBX_DESC_FW_CMPL	DESC_BIT(1)
#define FBNIC_IPC_MBX_DESC_HOST_CMPL	DESC_BIT(0)

#endif /* _FBNIC_CSR_H_ */