blob: ac4d4ea5159787018ff167ac83d94bae6076ac31 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
|
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
#ifndef _MLXSW_PORT_H
#define _MLXSW_PORT_H
#include <linux/types.h>
#define MLXSW_PORT_MAX_MTU 10000
#define MLXSW_PORT_DEFAULT_VID 1
#define MLXSW_PORT_SWID_DISABLED_PORT 255
#define MLXSW_PORT_SWID_ALL_SWIDS 254
#define MLXSW_PORT_SWID_TYPE_IB 1
#define MLXSW_PORT_SWID_TYPE_ETH 2
#define MLXSW_PORT_MAX_IB_PHY_PORTS 36
#define MLXSW_PORT_MAX_IB_PORTS (MLXSW_PORT_MAX_IB_PHY_PORTS + 1)
#define MLXSW_PORT_CPU_PORT 0x0
#define MLXSW_PORT_DONT_CARE 0xFF
enum mlxsw_port_admin_status {
MLXSW_PORT_ADMIN_STATUS_UP = 1,
MLXSW_PORT_ADMIN_STATUS_DOWN = 2,
MLXSW_PORT_ADMIN_STATUS_UP_ONCE = 3,
MLXSW_PORT_ADMIN_STATUS_DISABLED = 4,
};
enum mlxsw_reg_pude_oper_status {
MLXSW_PORT_OPER_STATUS_UP = 1,
MLXSW_PORT_OPER_STATUS_DOWN = 2,
MLXSW_PORT_OPER_STATUS_FAILURE = 4, /* Can be set to up again. */
};
#endif /* _MLXSW_PORT_H */
|
