1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
|
// SPDX-License-Identifier: GPL-1.0
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mt7986-clk.h>
#include <linux/clk.h>
static DEFINE_SPINLOCK(mt7986_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000),
};
static const struct mtk_fixed_factor top_divs[] = {
/* XTAL */
FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
/* MPLL */
FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
/* MMPLL */
FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4),
FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8),
FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16),
FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24),
FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30),
/* APLL2 */
FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
/* NET1PLL */
FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4),
FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5),
FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10),
FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20),
FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16),
FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32),
/* NET2PLL */
FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4),
FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8),
FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2),
/* WEDMCUPLL */
FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1,
10),
};
static const char *const nfi1x_parents[] __initconst = { "top_xtal",
"top_mmpll_d8",
"top_net1pll_d8_d2",
"top_net2pll_d3_d2",
"top_mpll_d4",
"top_mmpll_d8_d2",
"top_wedmcupll_d5_d2",
"top_mpll_d8" };
static const char *const spinfi_parents[] __initconst = {
"top_xtal_d2", "top_xtal", "top_net1pll_d5_d4",
"top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2",
"top_mmpll_d3_d8", "top_mpll_d8"
};
static const char *const spi_parents[] __initconst = {
"top_xtal", "top_mpll_d2", "top_mmpll_d8",
"top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4",
"top_mpll_d4", "top_wedmcupll_d5_d2"
};
static const char *const uart_parents[] __initconst = { "top_xtal",
"top_mpll_d8",
"top_mpll_d8_d2" };
static const char *const pwm_parents[] __initconst = {
"top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4"
};
static const char *const i2c_parents[] __initconst = {
"top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4"
};
static const char *const pextp_tl_ck_parents[] __initconst = {
"top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k"
};
static const char *const emmc_250m_parents[] __initconst = {
"top_xtal", "top_net1pll_d5_d2"
};
static const char *const emmc_416m_parents[] __initconst = { "top_xtal",
"mpll" };
static const char *const f_26m_adc_parents[] __initconst = { "top_xtal",
"top_mpll_d8_d2" };
static const char *const dramc_md32_parents[] __initconst = { "top_xtal",
"top_mpll_d2" };
static const char *const sysaxi_parents[] __initconst = { "top_xtal",
"top_net1pll_d8_d2",
"top_net2pll_d4" };
static const char *const sysapb_parents[] __initconst = { "top_xtal",
"top_mpll_d3_d2",
"top_net2pll_d4_d2" };
static const char *const arm_db_main_parents[] __initconst = {
"top_xtal", "top_net2pll_d3_d2"
};
static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag",
"top_xtal" };
static const char *const netsys_parents[] __initconst = { "top_xtal",
"top_mmpll_d4" };
static const char *const netsys_500m_parents[] __initconst = {
"top_xtal", "top_net1pll_d5"
};
static const char *const netsys_mcu_parents[] __initconst = {
"top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4",
"top_net1pll_d5"
};
static const char *const netsys_2x_parents[] __initconst = {
"top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2"
};
static const char *const sgm_325m_parents[] __initconst = { "top_xtal",
"sgmpll" };
static const char *const sgm_reg_parents[] __initconst = {
"top_xtal", "top_net1pll_d8_d4"
};
static const char *const a1sys_parents[] __initconst = { "top_xtal",
"top_apll2_d4" };
static const char *const conn_mcusys_parents[] __initconst = { "top_xtal",
"top_mmpll_d2" };
static const char *const eip_b_parents[] __initconst = { "top_xtal",
"net2pll" };
static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2",
"top_mpll_d8_d2" };
static const char *const a_tuner_parents[] __initconst = { "top_xtal",
"top_apll2_d4",
"top_mpll_d8_d2" };
static const char *const u2u3_sys_parents[] __initconst = {
"top_xtal", "top_net1pll_d5_d4"
};
static const char *const da_u2_refsel_parents[] __initconst = {
"top_xtal", "top_mmpll_u2phy"
};
static const struct mtk_mux top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
0x004, 0x008, 16, 3, 23, 0x1C0, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
0x014, 0x018, 0, 2, 7, 0x1C0, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
0x014, 0x018, 8, 2, 15, 0x1C0, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
0x014, 0x018, 16, 2, 23, 0x1C0, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
31, 0x1C0, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
0x1C0, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
0x1C0, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
0x1C0, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
0x1C0, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
31, 0x1C0, 15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel",
arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7,
0x1C0, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1,
23, 0x1C0, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
0x1C0, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
0x1C0, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
0x1C0, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
0x1C0, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel",
conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7,
0x1C0, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents,
0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel",
f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23,
0x1C0, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
0x1C0, 27),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
0x1C0, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23,
0x1C0, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents,
0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7,
0x1C4, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15,
0x1C4, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel",
da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1,
23, 0x1C4, 3),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel",
da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1,
31, 0x1C4, 4),
/* CLK_CFG_9 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7,
0x1C4, 5),
};
static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
void __iomem *base;
int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
ARRAY_SIZE(top_muxes);
base = of_iomap(node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
return -ENOMEM;
}
clk_data = mtk_alloc_clk_data(nr);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
&mt7986_clk_lock, clk_data);
clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r) {
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
goto free_topckgen_data;
}
return r;
free_topckgen_data:
mtk_free_clk_data(clk_data);
return r;
}
static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
{ .compatible = "mediatek,mt7986-topckgen", },
{}
};
static struct platform_driver clk_mt7986_topckgen_drv = {
.probe = clk_mt7986_topckgen_probe,
.driver = {
.name = "clk-mt7986-topckgen",
.of_match_table = of_match_clk_mt7986_topckgen,
},
};
builtin_platform_driver(clk_mt7986_topckgen_drv);
|
