blob: 107f743fbb1c304b9941c41b31a8c90450a6479f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Jens Lang <j.lang@phytec.de>
*
* Tauri-L RS232 with RTS/CTS hardware flow control:
* - UART4_TX becomes RTS
* - UART4_RX becomes CTS
*/
#include <dt-bindings/clock/imx8mm-clock.h>
#include "imx8mm-pinfunc.h"
/dts-v1/;
/plugin/;
&{/} {
compatible = "phytec,imx8mm-phygate-tauri-l";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&iomuxc {
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x00
MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x00
>;
};
};
|
