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|
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM memory mapped architected timer
maintainers:
- Marc Zyngier <marc.zyngier@arm.com>
- Mark Rutland <mark.rutland@arm.com>
description: |+
ARM cores may have a memory mapped architected timer, which provides up to 8
frames with a physical and optional virtual timer per frame.
The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
properties:
compatible:
items:
- enum:
- arm,armv7-timer-mem
reg:
maxItems: 1
description: The control frame base address
'#address-cells':
enum: [1, 2]
'#size-cells':
const: 1
ranges: true
clock-frequency:
description: The frequency of the main counter, in Hz. Should be present
only where necessary to work around broken firmware which does not configure
CNTFRQ on all CPUs to a uniform correct value. Use of this property is
strongly discouraged; fix your firmware unless absolutely impossible.
always-on:
type: boolean
description: If present, the timer is powered through an always-on power
domain, therefore it never loses context.
arm,cpu-registers-not-fw-configured:
type: boolean
description: Firmware does not initialize any of the generic timer CPU
registers, which contain their architecturally-defined reset values. Only
supported for 32-bit systems which follow the ARMv7 architected reset
values.
arm,no-tick-in-suspend:
type: boolean
description: The main counter does not tick when the system is in
low-power system suspend on some SoCs. This behavior does not match the
Architecture Reference Manual's specification that the system counter "must
be implemented in an always-on power domain."
patternProperties:
'^frame@[0-9a-z]*$':
type: object
description: A timer node has up to 8 frame sub-nodes, each with the following properties.
properties:
frame-number:
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 7
interrupts:
minItems: 1
items:
- description: physical timer irq
- description: virtual timer irq
reg:
minItems: 1
items:
- description: 1st view base address
- description: 2nd optional view base address
required:
- frame-number
- interrupts
- reg
required:
- compatible
- reg
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
timer@f0000000 {
compatible = "arm,armv7-timer-mem";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xf0001000 0x1000>;
reg = <0xf0000000 0x1000>;
clock-frequency = <50000000>;
frame@0 {
frame-number = <0>;
interrupts = <0 13 0x8>,
<0 14 0x8>;
reg = <0x0000 0x1000>,
<0x1000 0x1000>;
};
frame@2000 {
frame-number = <1>;
interrupts = <0 15 0x8>;
reg = <0x2000 0x1000>;
};
};
...
|
