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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PD692x0 Power Sourcing Equipment controller
maintainers:
- Kory Maincent <kory.maincent@bootlin.com>
allOf:
- $ref: pse-controller.yaml#
properties:
compatible:
enum:
- microchip,pd69200
- microchip,pd69210
- microchip,pd69220
reg:
maxItems: 1
managers:
type: object
additionalProperties: false
description:
List of the PD69208T4/PD69204T4/PD69208M PSE managers. Each manager
have 4 or 8 physical ports according to the chip version. No need to
specify the SPI chip select as it is automatically detected by the
PD692x0 PSE controller. The PSE managers have to be described from
the lowest chip select to the greatest one, which is the detection
behavior of the PD692x0 PSE controller. The PD692x0 support up to
12 PSE managers which can expose up to 96 physical ports. All
physical ports available on a manager have to be described in the
incremental order even if they are not used.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
required:
- "#address-cells"
- "#size-cells"
patternProperties:
"^manager@[0-9a-b]$":
type: object
additionalProperties: false
description:
PD69208T4/PD69204T4/PD69208M PSE manager exposing 4 or 8 physical
ports.
properties:
reg:
description:
Incremental index of the PSE manager starting from 0, ranging
from lowest to highest chip select, up to 11.
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
'^port@[0-7]$':
type: object
additionalProperties: false
properties:
reg:
maxItems: 1
required:
- reg
required:
- reg
- "#address-cells"
- "#size-cells"
required:
- compatible
- reg
- pse-pis
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
ethernet-pse@3c {
compatible = "microchip,pd69200";
reg = <0x3c>;
managers {
#address-cells = <1>;
#size-cells = <0>;
manager@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
phys0: port@0 {
reg = <0>;
};
phys1: port@1 {
reg = <1>;
};
phys2: port@2 {
reg = <2>;
};
phys3: port@3 {
reg = <3>;
};
};
manager@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
phys4: port@0 {
reg = <0>;
};
phys5: port@1 {
reg = <1>;
};
phys6: port@2 {
reg = <2>;
};
phys7: port@3 {
reg = <3>;
};
};
};
pse-pis {
#address-cells = <1>;
#size-cells = <0>;
pse_pi0: pse-pi@0 {
reg = <0>;
#pse-cells = <0>;
pairset-names = "alternative-a", "alternative-b";
pairsets = <&phys0>, <&phys1>;
polarity-supported = "MDI", "S";
vpwr-supply = <&vpwr1>;
};
pse_pi1: pse-pi@1 {
reg = <1>;
#pse-cells = <0>;
pairset-names = "alternative-a";
pairsets = <&phys2>;
polarity-supported = "MDI";
vpwr-supply = <&vpwr2>;
};
};
};
};
|
