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path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)Author
2014-12-10drm/i915/bdw: Fix the write setting up the WIZ hashing modeDamien Lespiau
2014-11-20drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersaveImre Deak
2014-11-20drm/i915: vlv: increase timeout when setting idle GPU freqImre Deak
2014-11-20drm/i915: Update ring freq for full gpu freq rangeTom O'Rourke
2014-11-20drm/i915: change initial rps frequency for gen8Tom O'Rourke
2014-11-20drm/i915: Keep min freq above floor on HSW/BDWTom O'Rourke
2014-11-20drm/i915: Use efficient frequency for HSW/BDWTom O'Rourke
2014-11-19Merge tag 'drm-intel-fixes-2014-11-19' into drm-intel-next-queuedDaniel Vetter
2014-11-19drm/i915: disable rps irqs earlier during suspend/unloadImre Deak
2014-11-19drm/i915: sanitize rps irq disablingImre Deak
2014-11-19drm/i915: sanitize rps irq enablingImre Deak
2014-11-19drm/i915: move rps irq disable one level upImre Deak
2014-11-19drm/i915: Extend pcode mailbox interfaceTom O'Rourke
2014-11-17drm/i915: Change CHV SKU400 GPU freq divider to 10Ville Syrjälä
2014-11-17drm/i915: Add missing newline to 'DDR speed' debug messagesVille Syrjälä
2014-11-17drm/i915: Refactor vlv/chv GPU frequency divider setupVille Syrjälä
2014-11-17drm/i915: Improve PCBR debug informationVille Syrjälä
2014-11-17drm/i915: Warn if GPLL isn't used on vlv/chvVille Syrjälä
2014-11-17drm/i915: Add a name for the Punit GPLLENABLE bitVille Syrjälä
2014-11-17drm/i915: Silence valleyview_set_rps()Ville Syrjälä
2014-11-17drm/i915: drop WaSetupGtModeTdRowDispatch:snbDaniel Vetter
2014-11-14drm/i915: Let's hope future platforms will use the same WM code as SKLDamien Lespiau
2014-11-14drm/i915: Clear PCODE_DATA1 on SNB+Damien Lespiau
2014-11-14drm/i915: Read the CCK fuse register from CCKVille Syrjälä
2014-11-14drm/i915: move rps irq enable/disable to i915_irq.cImre Deak
2014-11-14drm/i915: unify gen6/gen8 rps irq enable/disableImre Deak
2014-11-14drm/i915: unify gen6/gen8 pm irq helpersImre Deak
2014-11-14drm/i915/chv: Remove pre-production workaroundsArun Siluvery
2014-11-07drm/i915/skl: Enable Gen9 RC6Zhe Wang
2014-11-07drm/i915/skl: Log the order in which we flush the pipes in the WM codeDamien Lespiau
2014-11-07drm/i915/skl: Flush the WM configurationDamien Lespiau
2014-11-07drm/i915/skl: Stage the pipe DDB allocationDamien Lespiau
2014-11-07drm/i915/skl: Reduce the indentation level in skl_write_wm_values()Damien Lespiau
2014-11-07drm/i915/skl: Correctly align skl_compute_plane_wm() argumentsDamien Lespiau
2014-11-07drm/i915/skl: Rework when the transition WMs are computedDamien Lespiau
2014-11-07drm/i915/skl: Move all the WM compute functions in one placeDamien Lespiau
2014-11-07drm/i915/skl: Make res_blocks/lines intermediate values 32 bitsDamien Lespiau
2014-11-07drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm()Damien Lespiau
2014-11-07drm/i915/skl: Make 'end' of the DDB allocation entry exclusiveDamien Lespiau
2014-11-07drm/i915/skl: Check the DDB state at modesetDamien Lespiau
2014-11-07drm/i915/skl: Read back the DDB allocation hw stateDamien Lespiau
2014-11-07drm/i915/skl: Store the new WM state at the very end of the updateDamien Lespiau
2014-11-07drm/i915/gen9: Disable WM if corresponding latency is 0Vandana Kannan
2014-11-07drm/i915/gen9: Add 2us read latency to WM levelVandana Kannan
2014-11-07drm/i915/skl: Read the pipe WM HW statePradeep Bhat
2014-11-07drm/i915/skl: Program the DDB allocationDamien Lespiau
2014-11-07drm/i915/skl: Allocate DDB portions for display planesDamien Lespiau
2014-11-07drm/i915/skl: SKL Watermark ComputationPradeep Bhat
2014-11-07drm/i915/skl: Definition of SKL WM param structs for pipe/planePradeep Bhat
2014-11-07drm/i915/skl: Read the Memory Latency Values for WM computationPradeep Bhat
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