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path: root/drivers/clk/meson
AgeCommit message (Expand)Author
2023-11-24clk: meson: g12a: add CSI & ISP gates clocksNeil Armstrong
2023-11-24clk: meson: g12a: add MIPI ISP clocksNeil Armstrong
2023-11-24clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocksNeil Armstrong
2023-10-23clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILSArnd Bergmann
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controllerYu Tu
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC PLL clock driverYu Tu
2023-08-30Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2023-08-30Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd
2023-08-08clk: meson: axg-audio: move bindings include to main driverNeil Armstrong
2023-08-08clk: meson: meson8b: move bindings include to main driverNeil Armstrong
2023-08-08clk: meson: a1: move bindings include to main driverNeil Armstrong
2023-08-08clk: meson: eeclk: move bindings include to main driverNeil Armstrong
2023-08-08clk: meson: aoclk: move bindings include to main driverNeil Armstrong
2023-08-08dt-bindings: clk: axg-audio-clkc: expose all clock idsNeil Armstrong
2023-08-08dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock idsNeil Armstrong
2023-08-08dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock idsNeil Armstrong
2023-08-08dt-bindings: clk: meson8b-clkc: expose all clock idsNeil Armstrong
2023-08-08dt-bindings: clk: g12a-aoclkc: expose all clock idsNeil Armstrong
2023-08-08dt-bindings: clk: g12a-clks: expose all clock idsNeil Armstrong
2023-08-08dt-bindings: clk: axg-clkc: expose all clock idsNeil Armstrong
2023-08-08dt-bindings: clk: gxbb-clkc: expose all clock idsNeil Armstrong
2023-08-08clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKSNeil Armstrong
2023-08-08clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKSNeil Armstrong
2023-08-08clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKSNeil Armstrong
2023-08-08clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong
2023-08-08clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong
2023-08-08clk: meson: introduce meson-clkc-utilsNeil Armstrong
2023-07-19clk: Explicitly include correct DT includesRob Herring
2023-07-11clk: meson: change usleep_range() to udelay() for atomic contextDmitry Rokosov
2023-06-15clk: meson: pll: remove unneeded semicolonJiapeng Chong
2023-06-12clk: meson: a1: Staticize rtc clkStephen Boyd
2023-05-30clk: meson: a1: add Amlogic A1 Peripherals clock controller driverDmitry Rokosov
2023-05-30clk: meson: a1: add Amlogic A1 PLL clock controller driverDmitry Rokosov
2023-05-30clk: meson: introduce new pll power-on sequence for A1 SoC familyDmitry Rokosov
2023-05-30clk: meson: make pll rst bit as optionalDmitry Rokosov
2023-01-13clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rateMartin Blumenstingl
2023-01-13clk: meson: sclk-div: switch from .round_rate to .determine_rateMartin Blumenstingl
2023-01-13clk: meson: dualdiv: switch from .round_rate to .determine_rateMartin Blumenstingl
2023-01-13clk: meson: mpll: Switch from .round_rate to .determine_rateMartin Blumenstingl
2022-12-12Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' ...Stephen Boyd
2022-11-22clk: Remove a useless includeChristophe JAILLET
2022-11-08clk: meson: pll: add pcie lock retry workaroundHeiner Kallweit
2022-11-08clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()Heiner Kallweit
2022-08-19clk: meson: Hold reference returned by of_get_parent()Liang He
2022-06-15clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()Uwe Kleine-König
2022-03-11clk: cleanup commentsTom Rix
2021-11-30clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBBMartin Blumenstingl
2021-09-23clk: meson: meson8b: Make the video clock trees mutableMartin Blumenstingl
2021-09-23clk: meson: meson8b: Initialize the HDMI PLL registersMartin Blumenstingl
2021-09-23clk: meson: meson8b: Add the HDMI PLL M/N parametersMartin Blumenstingl