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path: root/arch/riscv/kernel/cpufeature.c
AgeCommit message (Expand)Author
2024-05-22riscv: cpufeature: Fix extension subset checkingCharlie Jenkins
2024-05-22riscv: cpufeature: Fix thead vector hwcap removalCharlie Jenkins
2024-03-22Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2024-03-13Merge patch series "riscv: Use Kconfig to set unaligned access speed"Palmer Dabbelt
2024-03-13riscv: Set unaligned access speed at compile timeCharlie Jenkins
2024-03-13riscv: Decouple emulated unaligned accesses from access speedCharlie Jenkins
2024-03-13riscv: lib: Introduce has_fast_unaligned_access()Charlie Jenkins
2024-03-12perf: RISC-V: Introduce Andes PMU to support perf event samplingYu Chien Peter Lin
2024-02-29Merge patch series "riscv: cbo.zero fixes"Palmer Dabbelt
2024-02-29riscv: Add a custom ISA extension for the [ms]envcfg CSRSamuel Holland
2024-02-29riscv: Fix enabling cbo.zero when running in M-modeSamuel Holland
2024-02-23RISC-V: Ignore V from the riscv,isa DT property on older T-Head CPUsConor Dooley
2024-01-17Merge patch series "riscv: Add fine-tuned checksum functions"Palmer Dabbelt
2024-01-17riscv: Add static key for misaligned accessesCharlie Jenkins
2024-01-09Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"Palmer Dabbelt
2024-01-09riscv: add ISA extension parsing for ZacasClément Léger
2024-01-09riscv: add ISA extension parsing for ZtsoClément Léger
2024-01-03RISC-V: Remove the removed single-letter extensionsPalmer Dabbelt
2023-12-12riscv: add ISA extension parsing for ZfaClément Léger
2023-12-12riscv: add ISA extension parsing for Zvfh[min]Clément Léger
2023-12-12riscv: add ISA extension parsing for ZihintntlClément Léger
2023-12-12riscv: add ISA extension parsing for Zfh/Zfh[min]Clément Léger
2023-12-12riscv: add ISA extension parsing for vector cryptoClément Léger
2023-12-12riscv: add ISA extension parsing for scalar cryptoEvan Green
2023-12-12riscv: add ISA extension parsing for ZbcClément Léger
2023-11-10Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2023-11-08Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2023-11-07RISC-V: Probe misaligned access speed in parallelEvan Green
2023-11-05riscv: don't probe unaligned access speed if already doneJisheng Zhang
2023-11-05Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt
2023-11-01riscv: report misaligned accesses emulation to hwprobeClément Léger
2023-11-01riscv: annotate check_unaligned_access_boot_cpu() with __initClément Léger
2023-10-31RISC-V: clarify the QEMU workaround in ISA parserTsukasa OI
2023-10-12RISC-V: Detect Zicond from ISA stringAnup Patel
2023-10-12RISC-V: Detect Smstateen extensionMayuresh Chitale
2023-09-21RISC-V: Enable cbo.zero in usermodeAndrew Jones
2023-09-21RISC-V: Make zicbom/zicboz errors consistentAndrew Jones
2023-09-08Merge patch series "RISC-V: Probe for misaligned access speed"Palmer Dabbelt
2023-09-01RISC-V: Probe for unaligned access speedEvan Green
2023-09-01Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2023-08-30Merge tag 'devicetree-header-cleanups-for-6.6' of git://git.kernel.org/pub/sc...Linus Torvalds
2023-08-28riscv: Explicitly include correct DT includesRob Herring
2023-07-25RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa"Conor Dooley
2023-07-25RISC-V: enable extension detection from dedicated propertiesConor Dooley
2023-07-25RISC-V: split riscv_fill_hwcap() in 3Conor Dooley
2023-07-25RISC-V: add single letter extensions to riscv_isa_extConor Dooley
2023-07-25RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()Conor Dooley
2023-07-25RISC-V: shunt isa_ext_arr to cpufeature.cConor Dooley
2023-07-12RISC-V: Don't include Zicsr or Zifencei in I from ACPIPalmer Dabbelt
2023-06-23Merge patch series "ISA string parser cleanups"Palmer Dabbelt