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path: root/arch/riscv/kernel/cpu.c
AgeCommit message (Expand)Author
2023-09-01Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2023-08-08riscv: Fix CPU feature detection with SMP disabledSamuel Holland
2023-08-02RISC-V: cpu: refactor deprecated strncpyJustin Stitt
2023-07-25RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa"Conor Dooley
2023-07-25RISC-V: try new extension properties in of_early_processor_hartid()Conor Dooley
2023-07-25RISC-V: add single letter extensions to riscv_isa_extConor Dooley
2023-07-25RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()Conor Dooley
2023-07-25RISC-V: shunt isa_ext_arr to cpufeature.cConor Dooley
2023-07-25RISC-V: drop a needless check in print_isa_ext()Conor Dooley
2023-07-25RISC-V: don't parse dt/acpi isa string to get rv32/rv64Heiko Stuebner
2023-07-25RISC-V: Provide a more helpful error message on invalid ISA stringsPalmer Dabbelt
2023-06-23Merge patch series "ISA string parser cleanups"Palmer Dabbelt
2023-06-21RISC-V: always report presence of extensions formerly part of the base ISAConor Dooley
2023-06-21RISC-V: validate riscv,isa at boot, not during ISA string parsingConor Dooley
2023-06-21RISC-V: split early & late of_node to hartid mappingConor Dooley
2023-06-19Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe"Palmer Dabbelt
2023-06-19RISC-V: Add Zba, Zbs extension probingEvan Green
2023-06-06Merge patch series "riscv: allow case-insensitive ISA string parsing"Palmer Dabbelt
2023-06-06riscv: allow case-insensitive ISA string parsingYangyu Chen
2023-06-01RISC-V: cpu: Enable cpuinfo for ACPI systemsSunil V L
2023-05-05Merge tag 'kvm-riscv-6.4-1' of https://github.com/kvm-riscv/linux into HEADPaolo Bonzini
2023-04-21RISC-V: Detect AIA CSRs from ISA stringAnup Patel
2023-04-18Merge patch series "RISC-V Hardware Probing User Interface"Palmer Dabbelt
2023-04-18RISC-V: Move struct riscv_cpuinfo to new headerEvan Green
2023-03-15Merge patch series "RISC-V: Apply Zicboz to clear_page"Palmer Dabbelt
2023-03-14RISC-V: Add Zicboz detection and block size parsingAndrew Jones
2023-03-09Merge patch series "riscv, mm: detect svnapot cpu support at runtime"Palmer Dabbelt
2023-03-07riscv: mm: modify pte format for SvnapotQinglin Pan
2023-02-21RISC-V: fix ordering of Zbb extensionHeiko Stuebner
2023-01-31RISC-V: add zbb support to string functionsHeiko Stuebner
2023-01-19Merge patch series "Putting some basic order on isa extension lists"Palmer Dabbelt
2023-01-17RISC-V: resort all extensions in consistent ordersConor Dooley
2023-01-17RISC-V: clarify ISA string ordering rules in cpu.cConor Dooley
2022-12-14Merge tag 'riscv-for-linus-6.2-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2022-10-27RISC-V: Fix /proc/cpuinfo cpumask warningAndrew Jones
2022-10-27RISC-V: Cache SBI vendor valuesHeiko Stuebner
2022-10-14Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2022-10-13RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputPalmer Dabbelt
2022-10-11Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
2022-10-06RISC-V: Print SSTC in canonical orderPalmer Dabbelt
2022-10-03RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputAnup Patel
2022-10-02RISC-V: Probe Svinval extension form ISA stringMayuresh Chitale
2022-08-11RISC-V: Add Sstc extension supportPalmer Dabbelt
2022-08-11RISC-V: Enable sstc extension parsing from DTAtish Patra
2022-08-11arch/riscv: add Zihintpause supportDao Lu
2022-08-10riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt
2022-07-28riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Sunil V L
2022-05-21riscv: Don't output a bogus mmu-type on a no MMU kernelNiklas Cassel
2022-05-11riscv: add RISC-V Svpbmt extension supportHeiko Stuebner