diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/arm/qcom,ids.h | 170 | ||||
| -rw-r--r-- | include/dt-bindings/clock/tegra234-clock.h | 639 | ||||
| -rw-r--r-- | include/dt-bindings/memory/tegra234-mc.h | 440 | ||||
| -rw-r--r-- | include/dt-bindings/power/qcom-rpmpd.h | 42 | ||||
| -rw-r--r-- | include/dt-bindings/power/tegra234-powergate.h | 15 | ||||
| -rw-r--r-- | include/dt-bindings/reset/tegra234-reset.h | 111 | ||||
| -rw-r--r-- | include/linux/bcm47xx_nvram.h | 6 | ||||
| -rw-r--r-- | include/linux/platform_data/gpmc-omap.h | 8 | ||||
| -rw-r--r-- | include/linux/pm_domain.h | 7 | ||||
| -rw-r--r-- | include/linux/soc/mediatek/mtk-mmsys.h | 7 | ||||
| -rw-r--r-- | include/linux/soc/qcom/llcc-qcom.h | 12 | ||||
| -rw-r--r-- | include/memory/renesas-rpc-if.h | 1 | ||||
| -rw-r--r-- | include/soc/fsl/qe/qe.h | 5 | ||||
| -rw-r--r-- | include/soc/qcom/qcom-spmi-pmic.h | 17 | ||||
| -rw-r--r-- | include/soc/tegra/bpmp-abi.h | 1796 | ||||
| -rw-r--r-- | include/soc/tegra/bpmp.h | 17 | ||||
| -rw-r--r-- | include/soc/tegra/fuse.h | 15 | ||||
| -rw-r--r-- | include/soc/tegra/ivc.h | 12 | ||||
| -rw-r--r-- | include/soc/tegra/pmc.h | 6 |
19 files changed, 2839 insertions, 487 deletions
diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h new file mode 100644 index 000000000000..f7aef3f310d7 --- /dev/null +++ b/include/dt-bindings/arm/qcom,ids.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> based on previous work of Kumar Gala. + */ +#ifndef _DT_BINDINGS_ARM_QCOM_IDS_H +#define _DT_BINDINGS_ARM_QCOM_IDS_H + +/* + * The MSM chipset and hardware revision used by Qualcomm bootloaders, DTS for + * older chipsets (qcom,msm-id) and in socinfo driver: + */ +#define QCOM_ID_MSM8960 87 +#define QCOM_ID_APQ8064 109 +#define QCOM_ID_MSM8660A 122 +#define QCOM_ID_MSM8260A 123 +#define QCOM_ID_APQ8060A 124 +#define QCOM_ID_MSM8974 126 +#define QCOM_ID_MPQ8064 130 +#define QCOM_ID_MSM8960AB 138 +#define QCOM_ID_APQ8060AB 139 +#define QCOM_ID_MSM8260AB 140 +#define QCOM_ID_MSM8660AB 141 +#define QCOM_ID_MSM8626 145 +#define QCOM_ID_MSM8610 147 +#define QCOM_ID_APQ8064AB 153 +#define QCOM_ID_MSM8226 158 +#define QCOM_ID_MSM8526 159 +#define QCOM_ID_MSM8110 161 +#define QCOM_ID_MSM8210 162 +#define QCOM_ID_MSM8810 163 +#define QCOM_ID_MSM8212 164 +#define QCOM_ID_MSM8612 165 +#define QCOM_ID_MSM8112 166 +#define QCOM_ID_MSM8225Q 168 +#define QCOM_ID_MSM8625Q 169 +#define QCOM_ID_MSM8125Q 170 +#define QCOM_ID_APQ8064AA 172 +#define QCOM_ID_APQ8084 178 +#define QCOM_ID_APQ8074 184 +#define QCOM_ID_MSM8274 185 +#define QCOM_ID_MSM8674 186 +#define QCOM_ID_MSM8974PRO_AC 194 +#define QCOM_ID_MSM8126 198 +#define QCOM_ID_APQ8026 199 +#define QCOM_ID_MSM8926 200 +#define QCOM_ID_MSM8326 205 +#define QCOM_ID_MSM8916 206 +#define QCOM_ID_MSM8994 207 +#define QCOM_ID_APQ8074PRO_AA 208 +#define QCOM_ID_APQ8074PRO_AB 209 +#define QCOM_ID_APQ8074PRO_AC 210 +#define QCOM_ID_MSM8274PRO_AA 211 +#define QCOM_ID_MSM8274PRO_AB 212 +#define QCOM_ID_MSM8274PRO_AC 213 +#define QCOM_ID_MSM8674PRO_AA 214 +#define QCOM_ID_MSM8674PRO_AB 215 +#define QCOM_ID_MSM8674PRO_AC 216 +#define QCOM_ID_MSM8974PRO_AA 217 +#define QCOM_ID_MSM8974PRO_AB 218 +#define QCOM_ID_APQ8028 219 +#define QCOM_ID_MSM8128 220 +#define QCOM_ID_MSM8228 221 +#define QCOM_ID_MSM8528 222 +#define QCOM_ID_MSM8628 223 +#define QCOM_ID_MSM8928 224 +#define QCOM_ID_MSM8510 225 +#define QCOM_ID_MSM8512 226 +#define QCOM_ID_MSM8936 233 +#define QCOM_ID_MSM8939 239 +#define QCOM_ID_APQ8036 240 +#define QCOM_ID_APQ8039 241 +#define QCOM_ID_MSM8996 246 +#define QCOM_ID_APQ8016 247 +#define QCOM_ID_MSM8216 248 +#define QCOM_ID_MSM8116 249 +#define QCOM_ID_MSM8616 250 +#define QCOM_ID_MSM8992 251 +#define QCOM_ID_APQ8094 253 +#define QCOM_ID_MSM8956 266 +#define QCOM_ID_MSM8976 278 +#define QCOM_ID_MDM9607 290 +#define QCOM_ID_APQ8096 291 +#define QCOM_ID_MSM8998 292 +#define QCOM_ID_MSM8953 293 +#define QCOM_ID_MDM8207 296 +#define QCOM_ID_MDM9207 297 +#define QCOM_ID_MDM9307 298 +#define QCOM_ID_MDM9628 299 +#define QCOM_ID_APQ8053 304 +#define QCOM_ID_MSM8996SG 305 +#define QCOM_ID_MSM8996AU 310 +#define QCOM_ID_APQ8096AU 311 +#define QCOM_ID_APQ8096SG 312 +#define QCOM_ID_SDM660 317 +#define QCOM_ID_SDM630 318 +#define QCOM_ID_APQ8098 319 +#define QCOM_ID_SDM845 321 +#define QCOM_ID_MDM9206 322 +#define QCOM_ID_IPQ8074 323 +#define QCOM_ID_SDA660 324 +#define QCOM_ID_SDM658 325 +#define QCOM_ID_SDA658 326 +#define QCOM_ID_SDA630 327 +#define QCOM_ID_SDM450 338 +#define QCOM_ID_SM8150 339 +#define QCOM_ID_SDA845 341 +#define QCOM_ID_IPQ8072 342 +#define QCOM_ID_IPQ8076 343 +#define QCOM_ID_IPQ8078 344 +#define QCOM_ID_SDM636 345 +#define QCOM_ID_SDA636 346 +#define QCOM_ID_SDM632 349 +#define QCOM_ID_SDA632 350 +#define QCOM_ID_SDA450 351 +#define QCOM_ID_SM8250 356 +#define QCOM_ID_SA8155 362 +#define QCOM_ID_IPQ8070 375 +#define QCOM_ID_IPQ8071 376 +#define QCOM_ID_IPQ8072A 389 +#define QCOM_ID_IPQ8074A 390 +#define QCOM_ID_IPQ8076A 391 +#define QCOM_ID_IPQ8078A 392 +#define QCOM_ID_SM6125 394 +#define QCOM_ID_IPQ8070A 395 +#define QCOM_ID_IPQ8071A 396 +#define QCOM_ID_IPQ6018 402 +#define QCOM_ID_IPQ6028 403 +#define QCOM_ID_SM4250 417 +#define QCOM_ID_IPQ6000 421 +#define QCOM_ID_IPQ6010 422 +#define QCOM_ID_SC7180 425 +#define QCOM_ID_SM6350 434 +#define QCOM_ID_SM8350 439 +#define QCOM_ID_SM6115 444 +#define QCOM_ID_SC8280XP 449 +#define QCOM_ID_IPQ6005 453 +#define QCOM_ID_QRB5165 455 +#define QCOM_ID_SM8450 457 +#define QCOM_ID_SM7225 459 +#define QCOM_ID_SA8295P 460 +#define QCOM_ID_SA8540P 461 +#define QCOM_ID_QCM4290 469 +#define QCOM_ID_QCS4290 470 +#define QCOM_ID_SM8450_2 480 +#define QCOM_ID_SM8450_3 482 +#define QCOM_ID_SC7280 487 +#define QCOM_ID_SC7180P 495 +#define QCOM_ID_SM6375 507 +#define QCOM_ID_SM8550 519 +#define QCOM_ID_QRU1000 539 +#define QCOM_ID_QDU1000 545 +#define QCOM_ID_QDU1010 587 +#define QCOM_ID_QRU1032 588 +#define QCOM_ID_QRU1052 589 +#define QCOM_ID_QRU1062 590 + +/* + * The board type and revision information, used by Qualcomm bootloaders and + * DTS for older chipsets (qcom,board-id): + */ +#define QCOM_BOARD_ID(a, major, minor) \ + (((major & 0xff) << 16) | ((minor & 0xff) << 8) | QCOM_BOARD_ID_##a) + +#define QCOM_BOARD_ID_MTP 8 +#define QCOM_BOARD_ID_DRAGONBOARD 10 +#define QCOM_BOARD_ID_SBC 24 + +#endif /* _DT_BINDINGS_ARM_QCOM_IDS_H */ diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 173364a93381..c360455d02ee 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -9,6 +9,12 @@ * @defgroup bpmp_clock_ids Clock ID's * @{ */ +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */ +#define TEGRA234_CLK_ACTMON 1U +/** @brief output of gate CLK_ENB_ADSP */ +#define TEGRA234_CLK_ADSP 2U +/** @brief output of gate CLK_ENB_ADSPNEON */ +#define TEGRA234_CLK_ADSPNEON 3U /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ #define TEGRA234_CLK_AHUB 4U /** @brief output of gate CLK_ENB_APB2APE */ @@ -17,6 +23,18 @@ #define TEGRA234_CLK_APE 6U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ #define TEGRA234_CLK_AUD_MCLK 7U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ +#define TEGRA234_CLK_AXI_CBB 8U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ +#define TEGRA234_CLK_CAN1 9U +/** @brief output of gate CLK_ENB_CAN1_HOST */ +#define TEGRA234_CLK_CAN1_HOST 10U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ +#define TEGRA234_CLK_CAN2 11U +/** @brief output of gate CLK_ENB_CAN2_HOST */ +#define TEGRA234_CLK_CAN2_HOST 12U +/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ +#define TEGRA234_CLK_CLK_M 14U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ #define TEGRA234_CLK_DMIC1 15U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ @@ -25,6 +43,28 @@ #define TEGRA234_CLK_DMIC3 17U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ #define TEGRA234_CLK_DMIC4 18U +/** @brief output of gate CLK_ENB_DPAUX */ +#define TEGRA234_CLK_DPAUX 19U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG1 */ +#define TEGRA234_CLK_NVJPG1 20U +/** + * @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY + * divided by the divider controlled by ACLK_CLK_DIVISOR in + * CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER + */ +#define TEGRA234_CLK_ACLK 21U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */ +#define TEGRA234_CLK_MSS_ENCRYPT 22U +/** @brief clock recovered from EAVB input */ +#define TEGRA234_CLK_EQOS_RX_INPUT 23U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */ +#define TEGRA234_CLK_AON_APB 25U +/** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */ +#define TEGRA234_CLK_AON_NIC 26U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */ +#define TEGRA234_CLK_AON_CPU_NIC 27U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ +#define TEGRA234_CLK_PLLA1 28U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ #define TEGRA234_CLK_DSPK1 29U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ @@ -38,10 +78,33 @@ * throughput and memory controller power. */ #define TEGRA234_CLK_EMC 31U -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ -#define TEGRA234_CLK_HOST1X 46U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */ +#define TEGRA234_CLK_EQOS_AXI 32U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */ +#define TEGRA234_CLK_EQOS_PTP_REF 33U +/** @brief output of gate CLK_ENB_EQOS_RX */ +#define TEGRA234_CLK_EQOS_RX 34U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */ +#define TEGRA234_CLK_EQOS_TX 35U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ +#define TEGRA234_CLK_EXTPERIPH1 36U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ +#define TEGRA234_CLK_EXTPERIPH2 37U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ +#define TEGRA234_CLK_EXTPERIPH3 38U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ +#define TEGRA234_CLK_EXTPERIPH4 39U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U +/** @brief output of GPU GPC0 clkGen (in 1x mode same rate as GPC0 MUX2 out) */ +#define TEGRA234_CLK_GPC0CLK 41U +/** @brief TODO */ +#define TEGRA234_CLK_GPU_PWR 42U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ +#define TEGRA234_CLK_HOST1X 46U +/** @brief xusb_hs_hsicp_clk */ +#define TEGRA234_CLK_XUSB_HS_HSICP 47U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ #define TEGRA234_CLK_I2C1 48U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ @@ -82,10 +145,66 @@ #define TEGRA234_CLK_I2S6 66U /** @brief clock recovered from I2S6 input */ #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ +#define TEGRA234_CLK_ISP 69U +/** @brief Monitored branch of EQOS_RX clock */ +#define TEGRA234_CLK_EQOS_RX_M 70U +/** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */ +#define TEGRA234_CLK_MAUD 71U +/** @brief output of gate CLK_ENB_MIPI_CAL */ +#define TEGRA234_CLK_MIPI_CAL 72U +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ +#define TEGRA234_CLK_MPHY_CORE_PLL_FIXED 73U +/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ +#define TEGRA234_CLK_MPHY_L0_RX_ANA 74U +/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ +#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT 75U +/** @brief output of gate CLK_ENB_MPHY_L0_RX_SYMB */ +#define TEGRA234_CLK_MPHY_L0_RX_SYMB 76U +/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ +#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT 77U +/** @brief output of gate CLK_ENB_MPHY_L0_TX_SYMB */ +#define TEGRA234_CLK_MPHY_L0_TX_SYMB 78U +/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ +#define TEGRA234_CLK_MPHY_L1_RX_ANA 79U +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ +#define TEGRA234_CLK_MPHY_TX_1MHZ_REF 80U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ +#define TEGRA234_CLK_NVCSI 81U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ +#define TEGRA234_CLK_NVCSILP 82U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ +#define TEGRA234_CLK_NVDEC 83U +/** @brief CLK_RST_CONTROLLER_HUBCLK_OUT_SWITCH_DIVIDER switch divider output (hubclk) */ +#define TEGRA234_CLK_HUB 84U +/** @brief CLK_RST_CONTROLLER_DISPCLK_SWITCH_DIVIDER switch divider output (dispclk) */ +#define TEGRA234_CLK_DISP 85U +/** @brief RG_CLK_CTRL__0_DIV divider output (nvdisplay_p0_clk) */ +#define TEGRA234_CLK_NVDISPLAY_P0 86U +/** @brief RG_CLK_CTRL__1_DIV divider output (nvdisplay_p1_clk) */ +#define TEGRA234_CLK_NVDISPLAY_P1 87U +/** @brief DSC_CLK (DISPCLK รท 3) */ +#define TEGRA234_CLK_DSC 88U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ +#define TEGRA234_CLK_NVENC 89U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ +#define TEGRA234_CLK_NVJPG 90U +/** @brief input from Tegra's XTAL_IN */ +#define TEGRA234_CLK_OSC 91U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH switch divider output */ +#define TEGRA234_CLK_AON_TOUCH 92U /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ #define TEGRA234_CLK_PLLA 93U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ +#define TEGRA234_CLK_PLLAON 94U +/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ +#define TEGRA234_CLK_PLLE 100U +/** @brief PLLP vco output */ +#define TEGRA234_CLK_PLLP 101U /** @brief PLLP clk output */ #define TEGRA234_CLK_PLLP_OUT0 102U +/** Fixed frequency 960MHz PLL for USB and EAVB */ +#define TEGRA234_CLK_UTMIP_PLL 103U /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ #define TEGRA234_CLK_PLLA_OUT0 104U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ @@ -104,8 +223,50 @@ #define TEGRA234_CLK_PWM7 111U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ #define TEGRA234_CLK_PWM8 112U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC output */ +#define TEGRA234_CLK_RCE_CPU_NIC 113U +/** @brief CLK_RST_CONTROLLER_RCE_NIC_RATE divider output */ +#define TEGRA234_CLK_RCE_NIC 114U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW switch divider output */ +#define TEGRA234_CLK_AON_I2C_SLOW 117U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ +#define TEGRA234_CLK_SCE_CPU_NIC 118U +/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ +#define TEGRA234_CLK_SCE_NIC 119U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ +#define TEGRA234_CLK_SDMMC1 120U +/** @brief Logical clk for setting the UPHY PLL3 rate */ +#define TEGRA234_CLK_UPHY_PLL3 121U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ #define TEGRA234_CLK_SDMMC4 123U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */ +#define TEGRA234_CLK_SE 124U +/** @brief VPLL select for sor0_ref clk driven by disp_2clk_sor0_head_sel signal */ +#define TEGRA234_CLK_SOR0_PLL_REF 125U +/** @brief Output of mux controlled by disp_2clk_sor0_pll_ref_clk_safe signal (sor0_ref_clk) */ +#define TEGRA234_CLK_SOR0_REF 126U +/** @brief VPLL select for sor1_ref clk driven by disp_2clk_sor0_head_sel signal */ +#define TEGRA234_CLK_SOR1_PLL_REF 127U +/** @brief SOR_PLL_REF_CLK_CTRL__0_DIV divider output */ +#define TEGRA234_CLK_PRE_SOR0_REF 128U +/** @brief Output of mux controlled by disp_2clk_sor1_pll_ref_clk_safe signal (sor1_ref_clk) */ +#define TEGRA234_CLK_SOR1_REF 129U +/** @brief SOR_PLL_REF_CLK_CTRL__1_DIV divider output */ +#define TEGRA234_CLK_PRE_SOR1_REF 130U +/** @brief output of gate CLK_ENB_SOR_SAFE */ +#define TEGRA234_CLK_SOR_SAFE 131U +/** @brief SOR_CLK_CTRL__0_DIV divider output */ +#define TEGRA234_CLK_SOR0_DIV 132U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ +#define TEGRA234_CLK_DMIC5 134U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ +#define TEGRA234_CLK_SPI1 135U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ +#define TEGRA234_CLK_SPI2 136U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI3 */ +#define TEGRA234_CLK_SPI3 137U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ +#define TEGRA234_CLK_I2C_SLOW 138U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ #define TEGRA234_CLK_SYNC_DMIC1 139U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ @@ -130,28 +291,132 @@ #define TEGRA234_CLK_SYNC_I2S5 149U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ #define TEGRA234_CLK_SYNC_I2S6 150U +/** @brief controls MPHY_FORCE_LS_MODE upon enable & disable */ +#define TEGRA234_CLK_MPHY_FORCE_LS_MODE 151U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH0 */ +#define TEGRA234_CLK_TACH0 152U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ +#define TEGRA234_CLK_TSEC 153U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */ +#define TEGRA234_CLK_TSEC_PKA 154U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ #define TEGRA234_CLK_UARTA 155U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ +#define TEGRA234_CLK_UARTB 156U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ +#define TEGRA234_CLK_UARTC 157U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ +#define TEGRA234_CLK_UARTD 158U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ +#define TEGRA234_CLK_UARTE 159U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ +#define TEGRA234_CLK_UARTF 160U /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ #define TEGRA234_CLK_PEX1_C6_CORE 161U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ +#define TEGRA234_CLK_UART_FST_MIPI_CAL 162U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ +#define TEGRA234_CLK_UFSDEV_REF 163U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ +#define TEGRA234_CLK_UFSHC 164U +/** @brief output of gate CLK_ENB_USB2_TRK */ +#define TEGRA234_CLK_USB2_TRK 165U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ +#define TEGRA234_CLK_VI 166U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ -#define TEGRA234_CLK_VIC 167U +#define TEGRA234_CLK_VIC 167U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_CSITE switch divider output */ +#define TEGRA234_CLK_CSITE 168U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_IST switch divider output */ +#define TEGRA234_CLK_IST 169U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_IST_JTAG_REG_CLK_SEL */ +#define TEGRA234_CLK_JTAG_INTFC_PRE_CG 170U /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ #define TEGRA234_CLK_PEX2_C7_CORE 171U /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ #define TEGRA234_CLK_PEX2_C8_CORE 172U /** @brief output of gate CLK_ENB_PEX2_CORE_9 */ #define TEGRA234_CLK_PEX2_C9_CORE 173U +/** @brief dla0_falcon_clk */ +#define TEGRA234_CLK_DLA0_FALCON 174U +/** @brief dla0_core_clk */ +#define TEGRA234_CLK_DLA0_CORE 175U +/** @brief dla1_falcon_clk */ +#define TEGRA234_CLK_DLA1_FALCON 176U +/** @brief dla1_core_clk */ +#define TEGRA234_CLK_DLA1_CORE 177U +/** @brief Output of mux controlled by disp_2clk_sor0_clk_safe signal (sor0_clk) */ +#define TEGRA234_CLK_SOR0 178U +/** @brief Output of mux controlled by disp_2clk_sor1_clk_safe signal (sor1_clk) */ +#define TEGRA234_CLK_SOR1 179U +/** @brief DP macro feedback clock (same as LINKA_SYM CLKOUT) */ +#define TEGRA234_CLK_SOR_PAD_INPUT 180U +/** @brief Output of mux controlled by disp_2clk_h0_dsi_sel signal in sf0_clk path */ +#define TEGRA234_CLK_PRE_SF0 181U +/** @brief Output of mux controlled by disp_2clk_sf0_clk_safe signal (sf0_clk) */ +#define TEGRA234_CLK_SF0 182U +/** @brief Output of mux controlled by disp_2clk_sf1_clk_safe signal (sf1_clk) */ +#define TEGRA234_CLK_SF1 183U +/** @brief CLKOUT_AB output from DSI BRICK A (dsi_clkout_ab) */ +#define TEGRA234_CLK_DSI_PAD_INPUT 184U /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ #define TEGRA234_CLK_PEX2_C10_CORE 187U -/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTI switch divider output (uarti_r_clk) */ +#define TEGRA234_CLK_UARTI 188U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ switch divider output (uartj_r_clk) */ +#define TEGRA234_CLK_UARTJ 189U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH switch divider output */ +#define TEGRA234_CLK_UARTH 190U +/** @brief ungated version of fuse clk */ +#define TEGRA234_CLK_FUSE_SERIAL 191U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output (qspi0_2x_pm_clk) */ #define TEGRA234_CLK_QSPI0_2X_PM 192U -/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output (qspi1_2x_pm_clk) */ #define TEGRA234_CLK_QSPI1_2X_PM 193U -/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 (qspi0_pm_clk) */ #define TEGRA234_CLK_QSPI0_PM 194U -/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 (qspi1_pm_clk) */ #define TEGRA234_CLK_QSPI1_PM 195U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST switch divider output */ +#define TEGRA234_CLK_VI_CONST 196U +/** @brief NAFLL clock source for BPMP */ +#define TEGRA234_CLK_NAFLL_BPMP 197U +/** @brief NAFLL clock source for SCE */ +#define TEGRA234_CLK_NAFLL_SCE 198U +/** @brief NAFLL clock source for NVDEC */ +#define TEGRA234_CLK_NAFLL_NVDEC 199U +/** @brief NAFLL clock source for NVJPG */ +#define TEGRA234_CLK_NAFLL_NVJPG 200U +/** @brief NAFLL clock source for TSEC */ +#define TEGRA234_CLK_NAFLL_TSEC 201U +/** @brief NAFLL clock source for VI */ +#define TEGRA234_CLK_NAFLL_VI 203U +/** @brief NAFLL clock source for SE */ +#define TEGRA234_CLK_NAFLL_SE 204U +/** @brief NAFLL clock source for NVENC */ +#define TEGRA234_CLK_NAFLL_NVENC 205U +/** @brief NAFLL clock source for ISP */ +#define TEGRA234_CLK_NAFLL_ISP 206U +/** @brief NAFLL clock source for VIC */ +#define TEGRA234_CLK_NAFLL_VIC 207U +/** @brief NAFLL clock source for AXICBB */ +#define TEGRA234_CLK_NAFLL_AXICBB 209U +/** @brief NAFLL clock source for NVJPG1 */ +#define TEGRA234_CLK_NAFLL_NVJPG1 210U +/** @brief NAFLL clock source for PVA core */ +#define TEGRA234_CLK_NAFLL_PVA0_CORE 211U +/** @brief NAFLL clock source for PVA VPS */ +#define TEGRA234_CLK_NAFLL_PVA0_VPS 212U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0 switch divider output (dbgapb_clk) */ +#define TEGRA234_CLK_DBGAPB 213U +/** @brief NAFLL clock source for RCE */ +#define TEGRA234_CLK_NAFLL_RCE 214U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_LA switch divider output (la_r_clk) */ +#define TEGRA234_CLK_LA 215U +/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTD */ +#define TEGRA234_CLK_PLLP_OUT_JTAG 216U +/** @brief AXI_CBB branch sharing gate control with SDMMC4 */ +#define TEGRA234_CLK_SDMMC4_AXICIF 217U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ @@ -166,8 +431,42 @@ #define TEGRA234_CLK_PEX0_C4_CORE 224U /** @brief output of gate CLK_ENB_PEX1_CORE_5 */ #define TEGRA234_CLK_PEX1_C5_CORE 225U +/** @brief Monitored branch of PEX0_C0_CORE clock */ +#define TEGRA234_CLK_PEX0_C0_CORE_M 229U +/** @brief Monitored branch of PEX0_C1_CORE clock */ +#define TEGRA234_CLK_PEX0_C1_CORE_M 230U +/** @brief Monitored branch of PEX0_C2_CORE clock */ +#define TEGRA234_CLK_PEX0_C2_CORE_M 231U +/** @brief Monitored branch of PEX0_C3_CORE clock */ +#define TEGRA234_CLK_PEX0_C3_CORE_M 232U +/** @brief Monitored branch of PEX0_C4_CORE clock */ +#define TEGRA234_CLK_PEX0_C4_CORE_M 233U +/** @brief Monitored branch of PEX1_C5_CORE clock */ +#define TEGRA234_CLK_PEX1_C5_CORE_M 234U +/** @brief Monitored branch of PEX1_C6_CORE clock */ +#define TEGRA234_CLK_PEX1_C6_CORE_M 235U +/** @brief output of GPU GPC1 clkGen (in 1x mode same rate as GPC1 MUX2 out) */ +#define TEGRA234_CLK_GPC1CLK 236U /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ #define TEGRA234_CLK_PLLC4 237U +/** @brief PLLC4 VCO followed by DIV3 path */ +#define TEGRA234_CLK_PLLC4_OUT1 239U +/** @brief PLLC4 VCO followed by DIV5 path */ +#define TEGRA234_CLK_PLLC4_OUT2 240U +/** @brief output of the mux controlled by PLLC4_CLK_SEL */ +#define TEGRA234_CLK_PLLC4_MUXED 241U +/** @brief PLLC4 VCO followed by DIV2 path */ +#define TEGRA234_CLK_PLLC4_VCO_DIV2 242U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVHS_BASE */ +#define TEGRA234_CLK_PLLNVHS 243U +/** @brief Monitored branch of PEX2_C7_CORE clock */ +#define TEGRA234_CLK_PEX2_C7_CORE_M 244U +/** @brief Monitored branch of PEX2_C8_CORE clock */ +#define TEGRA234_CLK_PEX2_C8_CORE_M 245U +/** @brief Monitored branch of PEX2_C9_CORE clock */ +#define TEGRA234_CLK_PEX2_C9_CORE_M 246U +/** @brief Monitored branch of PEX2_C10_CORE clock */ +#define TEGRA234_CLK_PEX2_C10_CORE_M 247U /** @brief RX clock recovered from MGBE0 lane input */ #define TEGRA234_CLK_MGBE0_RX_INPUT 248U /** @brief RX clock recovered from MGBE1 lane input */ @@ -176,8 +475,185 @@ #define TEGRA234_CLK_MGBE2_RX_INPUT 250U /** @brief RX clock recovered from MGBE3 lane input */ #define TEGRA234_CLK_MGBE3_RX_INPUT 251U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP switch divider output */ +#define TEGRA234_CLK_PEX_SATA_USB_RX_BYP 254U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT switch divider output */ +#define TEGRA234_CLK_PEX_USB_PAD_PLL0_MGMT 255U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT switch divider output */ +#define TEGRA234_CLK_PEX_USB_PAD_PLL1_MGMT 256U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT switch divider output */ +#define TEGRA234_CLK_PEX_USB_PAD_PLL2_MGMT 257U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT switch divider output */ +#define TEGRA234_CLK_PEX_USB_PAD_PLL3_MGMT 258U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP switch divider output */ +#define TEGRA234_CLK_NVHS_RX_BYP_REF 263U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT switch divider output */ +#define TEGRA234_CLK_NVHS_PLL0_MGMT 264U +/** @brief xusb_core_dev_clk */ +#define TEGRA234_CLK_XUSB_CORE_DEV 265U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST switch divider output */ +#define TEGRA234_CLK_XUSB_CORE_MUX 266U +/** @brief xusb_core_host_clk */ +#define TEGRA234_CLK_XUSB_CORE_HOST 267U +/** @brief xusb_core_superspeed_clk */ +#define TEGRA234_CLK_XUSB_CORE_SS 268U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON switch divider output */ +#define TEGRA234_CLK_XUSB_FALCON 269U +/** @brief xusb_falcon_host_clk */ +#define TEGRA234_CLK_XUSB_FALCON_HOST 270U +/** @brief xusb_falcon_superspeed_clk */ +#define TEGRA234_CLK_XUSB_FALCON_SS 271U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS switch divider output */ +#define TEGRA234_CLK_XUSB_FS 272U +/** @brief xusb_fs_host_clk */ +#define TEGRA234_CLK_XUSB_FS_HOST 273U +/** @brief xusb_fs_dev_clk */ +#define TEGRA234_CLK_XUSB_FS_DEV 274U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS switch divider output */ +#define TEGRA234_CLK_XUSB_SS 275U +/** @brief xusb_ss_dev_clk */ +#define TEGRA234_CLK_XUSB_SS_DEV 276U +/** @brief xusb_ss_superspeed_clk */ +#define TEGRA234_CLK_XUSB_SS_SUPERSPEED 277U +/** @brief NAFLL clock source for CPU cluster 0 */ +#define TEGRA234_CLK_NAFLL_CLUSTER0 280U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER0_CORE 280U +/** @brief NAFLL clock source for CPU cluster 1 */ +#define TEGRA234_CLK_NAFLL_CLUSTER1 281U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER1_CORE 281U +/** @brief NAFLL clock source for CPU cluster 2 */ +#define TEGRA234_CLK_NAFLL_CLUSTER2 282U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER2_CORE 282U +/** @brief CLK_RST_CONTROLLER_CAN1_CORE_RATE divider output */ +#define TEGRA234_CLK_CAN1_CORE 284U +/** @brief CLK_RST_CONTROLLER_CAN2_CORE_RATE divider outputt */ +#define TEGRA234_CLK_CAN2_CORE 285U +/** @brief CLK_RST_CONTROLLER_PLLA1_OUT1 switch divider output */ +#define TEGRA234_CLK_PLLA1_OUT1 286U +/** @brief NVHS PLL hardware power sequencer (overrides 'manual' programming of PLL) */ +#define TEGRA234_CLK_PLLNVHS_HPS 287U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE */ +#define TEGRA234_CLK_PLLREFE_VCOOUT 288U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief Fixed 48MHz clock divided down from utmipll */ +#define TEGRA234_CLK_UTMIPLL_CLKOUT48 291U +/** @brief Fixed 480MHz clock divided down from utmipll */ +#define TEGRA234_CLK_UTMIPLL_CLKOUT480 292U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ +#define TEGRA234_CLK_PLLNVCSI 294U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI switch divider output */ +#define TEGRA234_CLK_PVA0_CPU_AXI 295U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS switch divider output */ +#define TEGRA234_CLK_PVA0_VPS 297U +/** @brief DLA0_CORE_NAFLL */ +#define TEGRA234_CLK_NAFLL_DLA0_CORE 299U +/** @brief DLA0_FALCON_NAFLL */ +#define TEGRA234_CLK_NAFLL_DLA0_FALCON 300U +/** @brief DLA1_CORE_NAFLL */ +#define TEGRA234_CLK_NAFLL_DLA1_CORE 301U +/** @brief DLA1_FALCON_NAFLL */ +#define TEGRA234_CLK_NAFLL_DLA1_FALCON 302U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ +#define TEGRA234_CLK_AON_UART_FST_MIPI_CAL 303U +/** @brief GPU system clock */ +#define TEGRA234_CLK_GPUSYS 304U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 */ +#define TEGRA234_CLK_I2C5 305U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider free running clk */ +#define TEGRA234_CLK_FR_SE 306U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC switch divider output */ +#define TEGRA234_CLK_BPMP_CPU_NIC 307U +/** @brief output of gate CLK_ENB_BPMP_CPU */ +#define TEGRA234_CLK_BPMP_CPU 308U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSC switch divider output */ +#define TEGRA234_CLK_TSC 309U +/** @brief output of mem pll A sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMC */ +#define TEGRA234_CLK_EMCSA_MPLL 310U +/** @brief output of mem pll B sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB */ +#define TEGRA234_CLK_EMCSB_MPLL 311U +/** @brief output of mem pll C sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC */ +#define TEGRA234_CLK_EMCSC_MPLL 312U +/** @brief output of mem pll D sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD */ +#define TEGRA234_CLK_EMCSD_MPLL 313U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ +#define TEGRA234_CLK_PLLC 314U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ +#define TEGRA234_CLK_PLLC2 315U +/** @brief CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER skip divider output */ +#define TEGRA234_CLK_TSC_REF 317U +/** @brief Dummy clock to ensure minimum SoC voltage for fuse burning */ +#define TEGRA234_CLK_FUSE_BURN 318U +/** @brief GBE PLL */ +#define TEGRA234_CLK_PLLGBE 319U +/** @brief GBE PLL hardware power sequencer */ +#define TEGRA234_CLK_PLLGBE_HPS 320U +/** @brief output of EMC CDB side A fixed (DIV4) divider */ +#define TEGRA234_CLK_EMCSA_EMC 321U +/** @brief output of EMC CDB side B fixed (DIV4) divider */ +#define TEGRA234_CLK_EMCSB_EMC 322U +/** @brief output of EMC CDB side C fixed (DIV4) divider */ +#define TEGRA234_CLK_EMCSC_EMC 323U +/** @brief output of EMC CDB side D fixed (DIV4) divider */ +#define TEGRA234_CLK_EMCSD_EMC 324U +/** @brief PLLE hardware power sequencer (overrides 'manual' programming of PLL) */ +#define TEGRA234_CLK_PLLE_HPS 326U +/** @brief CLK_ENB_PLLREFE_OUT gate output */ +#define TEGRA234_CLK_PLLREFE_VCOOUT_GATED 327U +/** @brief TEGRA234_CLK_SOR_SAFE clk source (PLLP_OUT0 divided by 17) */ +#define TEGRA234_CLK_PLLP_DIV17 328U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM switch divider output */ +#define TEGRA234_CLK_SOC_THERM 329U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSENSE switch divider output */ +#define TEGRA234_CLK_TSENSE 330U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider free running clk */ +#define TEGRA234_CLK_FR_SEU1 331U +/** @brief NAFLL clock source for OFA */ +#define TEGRA234_CLK_NAFLL_OFA 333U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_OFA switch divider output */ +#define TEGRA234_CLK_OFA 334U +/** @brief NAFLL clock source for SEU1 */ +#define TEGRA234_CLK_NAFLL_SEU1 335U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider gated output */ +#define TEGRA234_CLK_SEU1 336U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ +#define TEGRA234_CLK_SPI4 337U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI5 */ +#define TEGRA234_CLK_SPI5 338U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DCE_CPU_NIC */ +#define TEGRA234_CLK_DCE_CPU_NIC 339U +/** @brief output of divider CLK_RST_CONTROLLER_DCE_NIC_RATE */ +#define TEGRA234_CLK_DCE_NIC 340U +/** @brief NAFLL clock source for DCE */ +#define TEGRA234_CLK_NAFLL_DCE 341U +/** @brief Monitored branch of MPHY_L0_RX_ANA clock */ +#define TEGRA234_CLK_MPHY_L0_RX_ANA_M 342U +/** @brief Monitored branch of MPHY_L1_RX_ANA clock */ +#define TEGRA234_CLK_MPHY_L1_RX_ANA_M 343U +/** @brief ungated version of TX symbol clock after fixed 1/2 divider */ +#define TEGRA234_CLK_MPHY_L0_TX_PRE_SYMB 344U +/** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ +#define TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV 345U +/** @brief output of gate CLK_ENB_MPHY_L0_TX_2X_SYMB */ +#define TEGRA234_CLK_MPHY_L0_TX_2X_SYMB 346U +/** @brief output of SW_MPHY_L0_TX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV 347U +/** @brief output of SW_MPHY_L0_TX_LS_3XBIT divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV 348U +/** @brief LS/HS divider mux SW_MPHY_L0_TX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV 349U +/** @brief Monitored branch of MPHY_L0_TX_SYMB clock */ +#define TEGRA234_CLK_MPHY_L0_TX_SYMB_M 350U +/** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ +#define TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV 351U +/** @brief output of SW_MPHY_L0_RX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV 352U +/** @brief output of SW_MPHY_L0_RX_LS_BIT divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV 353U +/** @brief LS/HS divider mux SW_MPHY_L0_RX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV 354U +/** @brief Monitored branch of MPHY_L0_RX_SYMB clock */ +#define TEGRA234_CLK_MPHY_L0_RX_SYMB_M 355U /** @brief Monitored branch of MBGE0 RX input clock */ #define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U /** @brief Monitored branch of MBGE1 RX input clock */ @@ -194,6 +670,14 @@ #define TEGRA234_CLK_MGBE2_RX_PCS_M 363U /** @brief Monitored branch of MGBE3 RX PCS mux output */ #define TEGRA234_CLK_MGBE3_RX_PCS_M 364U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH1 */ +#define TEGRA234_CLK_TACH1 365U +/** @brief GBE_UPHY_MGBES_APP_CLK switch divider gated output */ +#define TEGRA234_CLK_MGBES_APP 366U +/** @brief Logical clk for setting GBE UPHY PLL2 TX_REF rate */ +#define TEGRA234_CLK_UPHY_GBE_PLL2_TX_REF 367U +/** @brief Logical clk for setting GBE UPHY PLL2 XDIG rate */ +#define TEGRA234_CLK_UPHY_GBE_PLL2_XDIG 368U /** @brief RX PCS clock recovered from MGBE0 lane input */ #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U /** @brief RX PCS clock recovered from MGBE1 lane input */ @@ -230,6 +714,8 @@ #define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ #define TEGRA234_CLK_MGBE1_MAC 386U +/** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE1_MACSEC 387U /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ #define TEGRA234_CLK_MGBE1_EEE_PCS 388U /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ @@ -246,6 +732,8 @@ #define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ #define TEGRA234_CLK_MGBE2_MAC 395U +/** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE2_MACSEC 396U /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ #define TEGRA234_CLK_MGBE2_EEE_PCS 397U /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ @@ -270,9 +758,146 @@ #define TEGRA234_CLK_MGBE3_APP 407U /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ #define TEGRA234_CLK_MGBE3_PTP_REF 408U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_RX_BYP switch divider output */ +#define TEGRA234_CLK_GBE_RX_BYP_REF 409U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL0_MGMT switch divider output */ +#define TEGRA234_CLK_GBE_PLL0_MGMT 410U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL1_MGMT switch divider output */ +#define TEGRA234_CLK_GBE_PLL1_MGMT 411U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL2_MGMT switch divider output */ +#define TEGRA234_CLK_GBE_PLL2_MGMT 412U +/** @brief output of gate CLK_ENB_EQOS_MACSEC_RX */ +#define TEGRA234_CLK_EQOS_MACSEC_RX 413U +/** @brief output of gate CLK_ENB_EQOS_MACSEC_TX */ +#define TEGRA234_CLK_EQOS_MACSEC_TX 414U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider ungated output */ +#define TEGRA234_CLK_EQOS_TX_DIVIDER 415U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL1_MGMT switch divider output */ +#define TEGRA234_CLK_NVHS_PLL1_MGMT 416U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EMCHUB mux output */ +#define TEGRA234_CLK_EMCHUB 417U +/** @brief clock recovered from I2S7 input */ +#define TEGRA234_CLK_I2S7_SYNC_INPUT 418U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S7 */ +#define TEGRA234_CLK_SYNC_I2S7 419U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S7 */ +#define TEGRA234_CLK_I2S7 420U +/** @brief Monitored output of I2S7 pad macro mux */ +#define TEGRA234_CLK_I2S7_PAD_M 421U +/** @brief clock recovered from I2S8 input */ +#define TEGRA234_CLK_I2S8_SYNC_INPUT 422U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S8 */ +#define TEGRA234_CLK_SYNC_I2S8 423U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S8 */ +#define TEGRA234_CLK_I2S8 424U +/** @brief Monitored output of I2S8 pad macro mux */ +#define TEGRA234_CLK_I2S8_PAD_M 425U +/** @brief NAFLL clock source for GPU GPC0 */ +#define TEGRA234_CLK_NAFLL_GPC0 426U +/** @brief NAFLL clock source for GPU GPC1 */ +#define TEGRA234_CLK_NAFLL_GPC1 427U +/** @brief NAFLL clock source for GPU SYSCLK */ +#define TEGRA234_CLK_NAFLL_GPUSYS 428U +/** @brief NAFLL clock source for CPU cluster 0 DSUCLK */ +#define TEGRA234_CLK_NAFLL_DSU0 429U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER0_DSU 429U +/** @brief NAFLL clock source for CPU cluster 1 DSUCLK */ +#define TEGRA234_CLK_NAFLL_DSU1 430U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER1_DSU 430U +/** @brief NAFLL clock source for CPU cluster 2 DSUCLK */ +#define TEGRA234_CLK_NAFLL_DSU2 431U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER2_DSU 431U +/** @brief output of gate CLK_ENB_SCE_CPU */ +#define TEGRA234_CLK_SCE_CPU 432U +/** @brief output of gate CLK_ENB_RCE_CPU */ +#define TEGRA234_CLK_RCE_CPU 433U +/** @brief output of gate CLK_ENB_DCE_CPU */ +#define TEGRA234_CLK_DCE_CPU 434U +/** @brief DSIPLL VCO output */ +#define TEGRA234_CLK_DSIPLL_VCO 435U +/** @brief DSIPLL SYNC_CLKOUTP/N differential output */ +#define TEGRA234_CLK_DSIPLL_CLKOUTPN 436U +/** @brief DSIPLL SYNC_CLKOUTA output */ +#define TEGRA234_CLK_DSIPLL_CLKOUTA 437U +/** @brief SPPLL0 VCO output */ +#define TEGRA234_CLK_SPPLL0_VCO 438U +/** @brief SPPLL0 SYNC_CLKOUTP/N differential output */ +#define TEGRA234_CLK_SPPLL0_CLKOUTPN 439U +/** @brief SPPLL0 SYNC_CLKOUTA output */ +#define TEGRA234_CLK_SPPLL0_CLKOUTA 440U +/** @brief SPPLL0 SYNC_CLKOUTB output */ +#define TEGRA234_CLK_SPPLL0_CLKOUTB 441U +/** @brief SPPLL0 CLKOUT_DIVBY10 output */ +#define TEGRA234_CLK_SPPLL0_DIV10 442U +/** @brief SPPLL0 CLKOUT_DIVBY25 output */ +#define TEGRA234_CLK_SPPLL0_DIV25 443U +/** @brief SPPLL0 CLKOUT_DIVBY27P/N differential output */ +#define TEGRA234_CLK_SPPLL0_DIV27PN 444U +/** @brief SPPLL1 VCO output */ +#define TEGRA234_CLK_SPPLL1_VCO 445U +/** @brief SPPLL1 SYNC_CLKOUTP/N differential output */ +#define TEGRA234_CLK_SPPLL1_CLKOUTPN 446U +/** @brief SPPLL1 CLKOUT_DIVBY27P/N differential output */ +#define TEGRA234_CLK_SPPLL1_DIV27PN 447U +/** @brief VPLL0 reference clock */ +#define TEGRA234_CLK_VPLL0_REF 448U +/** @brief VPLL0 */ +#define TEGRA234_CLK_VPLL0 449U +/** @brief VPLL1 */ +#define TEGRA234_CLK_VPLL1 450U +/** @brief NVDISPLAY_P0_CLK reference select */ +#define TEGRA234_CLK_NVDISPLAY_P0_REF 451U +/** @brief RG0_PCLK */ +#define TEGRA234_CLK_RG0 452U +/** @brief RG1_PCLK */ +#define TEGRA234_CLK_RG1 453U +/** @brief DISPPLL output */ +#define TEGRA234_CLK_DISPPLL 454U +/** @brief DISPHUBPLL output */ +#define TEGRA234_CLK_DISPHUBPLL 455U +/** @brief CLK_RST_CONTROLLER_DSI_LP_SWITCH_DIVIDER switch divider output (dsi_lp_clk) */ +#define TEGRA234_CLK_DSI_LP 456U /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ #define TEGRA234_CLK_AZA_2XBIT 457U /** @brief aza_2xbitclk / 2 (aza_bitclk) */ #define TEGRA234_CLK_AZA_BIT 458U +/** @brief SWITCH_DSI_CORE_PIXEL_MISC_DSI_CORE_CLK_SRC switch output (dsi_core_clk) */ +#define TEGRA234_CLK_DSI_CORE 459U +/** @brief Output of mux controlled by pkt_wr_fifo_signal from dsi (dsi_pixel_clk) */ +#define TEGRA234_CLK_DSI_PIXEL 460U +/** @brief Output of mux controlled by disp_2clk_sor0_dp_sel (pre_sor0_clk) */ +#define TEGRA234_CLK_PRE_SOR0 461U +/** @brief Output of mux controlled by disp_2clk_sor1_dp_sel (pre_sor1_clk) */ +#define TEGRA234_CLK_PRE_SOR1 462U +/** @brief CLK_RST_CONTROLLER_LINK_REFCLK_CFG__0 output */ +#define TEGRA234_CLK_DP_LINK_REF 463U +/** @brief Link clock input from DP macro brick PLL */ +#define TEGRA234_CLK_SOR_LINKA_INPUT 464U +/** @brief SOR AFIFO clock outut */ +#define TEGRA234_CLK_SOR_LINKA_AFIFO 465U +/** @brief Monitored branch of linka_afifo_clk */ +#define TEGRA234_CLK_SOR_LINKA_AFIFO_M 466U +/** @brief Monitored branch of rg0_pclk */ +#define TEGRA234_CLK_RG0_M 467U +/** @brief Monitored branch of rg1_pclk */ +#define TEGRA234_CLK_RG1_M 468U +/** @brief Monitored branch of sor0_clk */ +#define TEGRA234_CLK_SOR0_M 469U +/** @brief Monitored branch of sor1_clk */ +#define TEGRA234_CLK_SOR1_M 470U +/** @brief EMC PLLHUB output */ +#define TEGRA234_CLK_PLLHUB 471U +/** @brief output of fixed (DIV2) MC HUB divider */ +#define TEGRA234_CLK_MCHUB 472U +/** @brief output of divider controlled by EMC side A MC_EMC_SAFE_SAME_FREQ */ +#define TEGRA234_CLK_EMCSA_MC 473U +/** @brief output of divider controlled by EMC side B MC_EMC_SAFE_SAME_FREQ */ +#define TEGRA234_CLK_EMCSB_MC 474U +/** @brief output of divider controlled by EMC side C MC_EMC_SAFE_SAME_FREQ */ +#define TEGRA234_CLK_EMCSC_MC 475U +/** @brief output of divider controlled by EMC side D MC_EMC_SAFE_SAME_FREQ */ +#define TEGRA234_CLK_EMCSD_MC 476U + +/** @} */ #endif diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index bd71cc1d7990..347e55e89a2a 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -8,31 +8,158 @@ #define TEGRA234_SID_INVALID 0x00 #define TEGRA234_SID_PASSTHROUGH 0x7f +/* ISO stream IDs */ +#define TEGRA234_SID_ISO_NVDISPLAY 0x01 +#define TEGRA234_SID_ISO_VI 0x02 +#define TEGRA234_SID_ISO_VIFALC 0x03 +#define TEGRA234_SID_ISO_VI2 0x04 +#define TEGRA234_SID_ISO_VI2FALC 0x05 +#define TEGRA234_SID_ISO_VI_VM2 0x06 +#define TEGRA234_SID_ISO_VI2_VM2 0x07 + /* NISO0 stream IDs */ -#define TEGRA234_SID_APE 0x02 -#define TEGRA234_SID_HDA 0x03 -#define TEGRA234_SID_GPCDMA 0x04 -#define TEGRA234_SID_MGBE 0x06 -#define TEGRA234_SID_PCIE0 0x12 -#define TEGRA234_SID_PCIE4 0x13 -#define TEGRA234_SID_PCIE5 0x14 -#define TEGRA234_SID_PCIE6 0x15 -#define TEGRA234_SID_PCIE9 0x1f -#define TEGRA234_SID_MGBE_VF1 0x49 -#define TEGRA234_SID_MGBE_VF2 0x4a -#define TEGRA234_SID_MGBE_VF3 0x4b +#define TEGRA234_SID_AON 0x01 +#define TEGRA234_SID_APE 0x02 +#define TEGRA234_SID_HDA 0x03 +#define TEGRA234_SID_GPCDMA 0x04 +#define TEGRA234_SID_ETR 0x05 +#define TEGRA234_SID_MGBE 0x06 +#define TEGRA234_SID_NVDISPLAY 0x07 +#define TEGRA234_SID_DCE 0x08 +#define TEGRA234_SID_PSC 0x09 +#define TEGRA234_SID_RCE 0x0a +#define TEGRA234_SID_SCE 0x0b +#define TEGRA234_SID_UFSHC 0x0c +#define TEGRA234_SID_APE_1 0x0d +#define TEGRA234_SID_GPCDMA_1 0x0e +#define TEGRA234_SID_GPCDMA_2 0x0f +#define TEGRA234_SID_GPCDMA_3 0x10 +#define TEGRA234_SID_GPCDMA_4 0x11 +#define TEGRA234_SID_PCIE0 0x12 +#define TEGRA234_SID_PCIE4 0x13 +#define TEGRA234_SID_PCIE5 0x14 +#define TEGRA234_SID_PCIE6 0x15 +#define TEGRA234_SID_RCE_VM2 0x16 +#define TEGRA234_SID_RCE_SERVER 0x17 +#define TEGRA234_SID_SMMU_TEST 0x18 +#define TEGRA234_SID_UFS_1 0x19 +#define TEGRA234_SID_UFS_2 0x1a +#define TEGRA234_SID_UFS_3 0x1b +#define TEGRA234_SID_UFS_4 0x1c +#define TEGRA234_SID_UFS_5 0x1d +#define TEGRA234_SID_UFS_6 0x1e +#define TEGRA234_SID_PCIE9 0x1f +#define TEGRA234_SID_VSE_GPCDMA_VM0 0x20 +#define TEGRA234_SID_VSE_GPCDMA_VM1 0x21 +#define TEGRA234_SID_VSE_GPCDMA_VM2 0x22 +#define TEGRA234_SID_NVDLA1 0x23 +#define TEGRA234_SID_NVENC 0x24 +#define TEGRA234_SID_NVJPG1 0x25 +#define TEGRA234_SID_OFA 0x26 +#define TEGRA234_SID_MGBE_VF1 0x49 +#define TEGRA234_SID_MGBE_VF2 0x4a +#define TEGRA234_SID_MGBE_VF3 0x4b +#define TEGRA234_SID_MGBE_VF4 0x4c +#define TEGRA234_SID_MGBE_VF5 0x4d +#define TEGRA234_SID_MGBE_VF6 0x4e +#define TEGRA234_SID_MGBE_VF7 0x4f +#define TEGRA234_SID_MGBE_VF8 0x50 +#define TEGRA234_SID_MGBE_VF9 0x51 +#define TEGRA234_SID_MGBE_VF10 0x52 +#define TEGRA234_SID_MGBE_VF11 0x53 +#define TEGRA234_SID_MGBE_VF12 0x54 +#define TEGRA234_SID_MGBE_VF13 0x55 +#define TEGRA234_SID_MGBE_VF14 0x56 +#define TEGRA234_SID_MGBE_VF15 0x57 +#define TEGRA234_SID_MGBE_VF16 0x58 +#define TEGRA234_SID_MGBE_VF17 0x59 +#define TEGRA234_SID_MGBE_VF18 0x5a +#define TEGRA234_SID_MGBE_VF19 0x5b +#define TEGRA234_SID_MGBE_VF20 0x5c +#define TEGRA234_SID_APE_2 0x5e +#define TEGRA234_SID_APE_3 0x5f +#define TEGRA234_SID_UFS_7 0x60 +#define TEGRA234_SID_UFS_8 0x61 +#define TEGRA234_SID_UFS_9 0x62 +#define TEGRA234_SID_UFS_10 0x63 +#define TEGRA234_SID_UFS_11 0x64 +#define TEGRA234_SID_UFS_12 0x65 +#define TEGRA234_SID_UFS_13 0x66 +#define TEGRA234_SID_UFS_14 0x67 +#define TEGRA234_SID_UFS_15 0x68 +#define TEGRA234_SID_UFS_16 0x69 +#define TEGRA234_SID_UFS_17 0x6a +#define TEGRA234_SID_UFS_18 0x6b +#define TEGRA234_SID_UFS_19 0x6c +#define TEGRA234_SID_UFS_20 0x6d +#define TEGRA234_SID_GPCDMA_5 0x6e +#define TEGRA234_SID_GPCDMA_6 0x6f +#define TEGRA234_SID_GPCDMA_7 0x70 +#define TEGRA234_SID_GPCDMA_8 0x71 +#define TEGRA234_SID_GPCDMA_9 0x72 /* NISO1 stream IDs */ -#define TEGRA234_SID_SDMMC4 0x02 -#define TEGRA234_SID_PCIE1 0x05 -#define TEGRA234_SID_PCIE2 0x06 -#define TEGRA234_SID_PCIE3 0x07 -#define TEGRA234_SID_PCIE7 0x08 -#define TEGRA234_SID_PCIE8 0x09 -#define TEGRA234_SID_PCIE10 0x0b -#define TEGRA234_SID_BPMP 0x10 -#define TEGRA234_SID_HOST1X 0x27 -#define TEGRA234_SID_VIC 0x34 +#define TEGRA234_SID_SDMMC1A 0x01 +#define TEGRA234_SID_SDMMC4 0x02 +#define TEGRA234_SID_EQOS 0x03 +#define TEGRA234_SID_HWMP_PMA 0x04 +#define TEGRA234_SID_PCIE1 0x05 +#define TEGRA234_SID_PCIE2 0x06 +#define TEGRA234_SID_PCIE3 0x07 +#define TEGRA234_SID_PCIE7 0x08 +#define TEGRA234_SID_PCIE8 0x09 +#define TEGRA234_SID_PCIE10 0x0b +#define TEGRA234_SID_QSPI0 0x0c +#define TEGRA234_SID_QSPI1 0x0d +#define TEGRA234_SID_XUSB_HOST 0x0e +#define TEGRA234_SID_XUSB_DEV 0x0f +#define TEGRA234_SID_BPMP 0x10 +#define TEGRA234_SID_FSI 0x11 +#define TEGRA234_SID_PVA0_VM0 0x12 +#define TEGRA234_SID_PVA0_VM1 0x13 +#define TEGRA234_SID_PVA0_VM2 0x14 +#define TEGRA234_SID_PVA0_VM3 0x15 +#define TEGRA234_SID_PVA0_VM4 0x16 +#define TEGRA234_SID_PVA0_VM5 0x17 +#define TEGRA234_SID_PVA0_VM6 0x18 +#define TEGRA234_SID_PVA0_VM7 0x19 +#define TEGRA234_SID_XUSB_VF0 0x1a +#define TEGRA234_SID_XUSB_VF1 0x1b +#define TEGRA234_SID_XUSB_VF2 0x1c +#define TEGRA234_SID_XUSB_VF3 0x1d +#define TEGRA234_SID_EQOS_VF1 0x1e +#define TEGRA234_SID_EQOS_VF2 0x1f +#define TEGRA234_SID_EQOS_VF3 0x20 +#define TEGRA234_SID_EQOS_VF4 0x21 +#define TEGRA234_SID_ISP_VM2 0x22 +#define TEGRA234_SID_HOST1X 0x27 +#define TEGRA234_SID_ISP 0x28 +#define TEGRA234_SID_NVDEC 0x29 +#define TEGRA234_SID_NVJPG 0x2a +#define TEGRA234_SID_NVDLA0 0x2b +#define TEGRA234_SID_PVA0 0x2c +#define TEGRA234_SID_SES_SE0 0x2d +#define TEGRA234_SID_SES_SE1 0x2e +#define TEGRA234_SID_SES_SE2 0x2f +#define TEGRA234_SID_SEU1_SE0 0x30 +#define TEGRA234_SID_SEU1_SE1 0x31 +#define TEGRA234_SID_SEU1_SE2 0x32 +#define TEGRA234_SID_TSEC 0x33 +#define TEGRA234_SID_VIC 0x34 +#define TEGRA234_SID_HC_VM0 0x3d +#define TEGRA234_SID_HC_VM1 0x3e +#define TEGRA234_SID_HC_VM2 0x3f +#define TEGRA234_SID_HC_VM3 0x40 +#define TEGRA234_SID_HC_VM4 0x41 +#define TEGRA234_SID_HC_VM5 0x42 +#define TEGRA234_SID_HC_VM6 0x43 +#define TEGRA234_SID_HC_VM7 0x44 +#define TEGRA234_SID_SE_VM0 0x45 +#define TEGRA234_SID_SE_VM1 0x46 +#define TEGRA234_SID_SE_VM2 0x47 +#define TEGRA234_SID_ISPFALC 0x48 +#define TEGRA234_SID_NISO1_SMMU_TEST 0x49 +#define TEGRA234_SID_TSEC_VM0 0x4a /* Shared stream IDs */ #define TEGRA234_SID_HOST1X_CTX0 0x35 @@ -48,21 +175,81 @@ * memory client IDs */ +/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ +#define TEGRA234_MEMORY_CLIENT_PTCR 0x00 +/* MSS internal memqual MIU7 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU7R 0x01 +/* MSS internal memqual MIU7 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU7W 0x02 +/* MSS internal memqual MIU8 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU8R 0x03 +/* MSS internal memqual MIU8 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU8W 0x04 +/* MSS internal memqual MIU9 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU9R 0x05 +/* MSS internal memqual MIU9 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU9W 0x06 +/* MSS internal memqual MIU10 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU10R 0x07 +/* MSS internal memqual MIU10 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU10W 0x08 +/* MSS internal memqual MIU11 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU11R 0x09 +/* MSS internal memqual MIU11 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU11W 0x0a +/* MSS internal memqual MIU12 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU12R 0x0b +/* MSS internal memqual MIU12 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU12W 0x0c +/* MSS internal memqual MIU13 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU13R 0x0d +/* MSS internal memqual MIU13 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU13W 0x0e +#define TEGRA234_MEMORY_CLIENT_NVL5RHP 0x13 +#define TEGRA234_MEMORY_CLIENT_NVL5R 0x14 /* High-definition audio (HDA) read clients */ #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 +/* Host channel data read clients */ #define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 +#define TEGRA234_MEMORY_CLIENT_NVL5W 0x17 +#define TEGRA234_MEMORY_CLIENT_NVL6RHP 0x18 +#define TEGRA234_MEMORY_CLIENT_NVL6R 0x19 +#define TEGRA234_MEMORY_CLIENT_NVL6W 0x1a +#define TEGRA234_MEMORY_CLIENT_NVL7RHP 0x1b +#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c +#define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d +#define TEGRA234_MEMORY_CLIENT_NVL7W 0x1e +#define TEGRA234_MEMORY_CLIENT_NVL8RHP 0x20 +#define TEGRA234_MEMORY_CLIENT_NVL8R 0x21 +#define TEGRA234_MEMORY_CLIENT_NVL8W 0x22 +#define TEGRA234_MEMORY_CLIENT_NVL9RHP 0x23 +#define TEGRA234_MEMORY_CLIENT_NVL9R 0x24 +#define TEGRA234_MEMORY_CLIENT_NVL9W 0x25 /* PCIE6 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 /* PCIE6 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 /* PCIE7 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a +#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b +/* DLA0ARDB read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c +/* DLA0ARDB1 read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d +/* DLA0 writes */ +#define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e +/* DLA1ARDB read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f /* PCIE7 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 /* PCIE8 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 /* High-definition audio (HDA) write clients */ #define TEGRA234_MEMORY_CLIENT_HDAW 0x35 +/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ +#define TEGRA234_MEMORY_CLIENT_MPCOREW 0x39 +/* OFAA client */ +#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a /* PCIE8 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b /* PCIE9 read clients */ @@ -75,10 +262,32 @@ #define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f /* PCIE10 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 +/* ISP read client for Crossbar A */ +#define TEGRA234_MEMORY_CLIENT_ISPRA 0x44 +/* ISP read client 1 for Crossbar A */ +#define TEGRA234_MEMORY_CLIENT_ISPFALR 0x45 +/* ISP Write client for Crossbar A */ +#define TEGRA234_MEMORY_CLIENT_ISPWA 0x46 +/* ISP Write client Crossbar B */ +#define TEGRA234_MEMORY_CLIENT_ISPWB 0x47 /* PCIE10r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 /* PCIE7r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 +/* XUSB_HOST read clients */ +#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTR 0x4a +/* XUSB_HOST write clients */ +#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTW 0x4b +/* XUSB read clients */ +#define TEGRA234_MEMORY_CLIENT_XUSB_DEVR 0x4c +/* XUSB_DEV write clients */ +#define TEGRA234_MEMORY_CLIENT_XUSB_DEVW 0x4d +/* TSEC Memory Return Data Client Description */ +#define TEGRA234_MEMORY_CLIENT_TSECSRD 0x54 +/* TSEC Memory Write Client Description */ +#define TEGRA234_MEMORY_CLIENT_TSECSWR 0x55 +/* XSPI writes */ +#define TEGRA234_MEMORY_CLIENT_XSPI1W 0x56 /* MGBE0 read client */ #define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 /* MGBEB read client */ @@ -89,18 +298,86 @@ #define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b /* MGBE0 write client */ #define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c +/* OFAA client */ +#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d +/* OFAA writes */ +#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e /* MGBEB write client */ #define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f +/* sdmmca memory read client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCRA 0x60 /* MGBEC write client */ #define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 +/* sdmmca memory write client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCWA 0x64 /* MGBED write client */ #define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 /* sdmmcd memory write client */ #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 +/* SE Memory Return Data Client Description */ +#define TEGRA234_MEMORY_CLIENT_SEU1RD 0x68 +/* SE Memory Write Client Description */ +#define TEGRA234_MEMORY_CLIENT_SUE1WR 0x69 #define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c #define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d +/* DLA1ARDB1 read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e +/* DLA1 writes */ +#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f +/* VI FLACON read clients */ +#define TEGRA234_MEMORY_CLIENT_VI2FALR 0x71 +/* VI Write client */ +#define TEGRA234_MEMORY_CLIENT_VI2W 0x70 +/* VI Write client */ +#define TEGRA234_MEMORY_CLIENT_VIW 0x72 +/* NISO display read client */ +#define TEGRA234_MEMORY_CLIENT_NVDISPNISOR 0x73 +/* NVDISPNISO writes */ +#define TEGRA234_MEMORY_CLIENT_NVDISPNISOW 0x74 +/* XSPI client */ +#define TEGRA234_MEMORY_CLIENT_XSPI0R 0x75 +/* XSPI writes */ +#define TEGRA234_MEMORY_CLIENT_XSPI0W 0x76 +/* XSPI client */ +#define TEGRA234_MEMORY_CLIENT_XSPI1R 0x77 +#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78 +#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79 +/* Audio Processing (APE) engine read clients */ +#define TEGRA234_MEMORY_CLIENT_APER 0x7a +/* Audio Processing (APE) engine write clients */ +#define TEGRA234_MEMORY_CLIENT_APEW 0x7b +/* VI2FAL writes */ +#define TEGRA234_MEMORY_CLIENT_VI2FALW 0x7c +#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e +#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f +/* SE Memory Return Data Client Description */ +#define TEGRA234_MEMORY_CLIENT_SESRD 0x80 +/* SE Memory Write Client Description */ +#define TEGRA234_MEMORY_CLIENT_SESWR 0x81 +/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ +#define TEGRA234_MEMORY_CLIENT_AXIAPR 0x82 +/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ +#define TEGRA234_MEMORY_CLIENT_AXIAPW 0x83 +/* ETR read clients */ +#define TEGRA234_MEMORY_CLIENT_ETRR 0x84 +/* ETR write clients */ +#define TEGRA234_MEMORY_CLIENT_ETRW 0x85 +/* AXI Switch read client */ +#define TEGRA234_MEMORY_CLIENT_AXISR 0x8c +/* AXI Switch write client */ +#define TEGRA234_MEMORY_CLIENT_AXISW 0x8d +/* EQOS read client */ +#define TEGRA234_MEMORY_CLIENT_EQOSR 0x8e +/* EQOS write client */ +#define TEGRA234_MEMORY_CLIENT_EQOSW 0x8f +/* UFSHC read client */ +#define TEGRA234_MEMORY_CLIENT_UFSHCR 0x90 +/* UFSHC write client */ +#define TEGRA234_MEMORY_CLIENT_UFSHCW 0x91 +/* NVDISPLAY read client */ +#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR 0x92 /* BPMP read client */ #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 /* BPMP write client */ @@ -109,10 +386,97 @@ #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 /* BPMPDMA write client */ #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 +/* AON read client */ +#define TEGRA234_MEMORY_CLIENT_AONR 0x97 +/* AON write client */ +#define TEGRA234_MEMORY_CLIENT_AONW 0x98 +/* AONDMA read client */ +#define TEGRA234_MEMORY_CLIENT_AONDMAR 0x99 +/* AONDMA write client */ +#define TEGRA234_MEMORY_CLIENT_AONDMAW 0x9a +/* SCE read client */ +#define TEGRA234_MEMORY_CLIENT_SCER 0x9b +/* SCE write client */ +#define TEGRA234_MEMORY_CLIENT_SCEW 0x9c +/* SCEDMA read client */ +#define TEGRA234_MEMORY_CLIENT_SCEDMAR 0x9d +/* SCEDMA write client */ +#define TEGRA234_MEMORY_CLIENT_SCEDMAW 0x9e /* APEDMA read client */ #define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f /* APEDMA write client */ #define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 +/* NVDISPLAY read client instance 2 */ +#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 0xa1 +#define TEGRA234_MEMORY_CLIENT_VICSRD1 0xa2 +/* MSS internal memqual MIU0 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU0R 0xa6 +/* MSS internal memqual MIU0 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU0W 0xa7 +/* MSS internal memqual MIU1 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU1R 0xa8 +/* MSS internal memqual MIU1 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU1W 0xa9 +/* MSS internal memqual MIU2 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU2R 0xae +/* MSS internal memqual MIU2 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU2W 0xaf +/* MSS internal memqual MIU3 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU3R 0xb0 +/* MSS internal memqual MIU3 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU3W 0xb1 +/* MSS internal memqual MIU4 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU4R 0xb2 +/* MSS internal memqual MIU4 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU4W 0xb3 +#define TEGRA234_MEMORY_CLIENT_DPMUR 0xb4 +#define TEGRA234_MEMORY_CLIENT_DPMUW 0xb5 +#define TEGRA234_MEMORY_CLIENT_NVL0R 0xb6 +#define TEGRA234_MEMORY_CLIENT_NVL0W 0xb7 +#define TEGRA234_MEMORY_CLIENT_NVL1R 0xb8 +#define TEGRA234_MEMORY_CLIENT_NVL1W 0xb9 +#define TEGRA234_MEMORY_CLIENT_NVL2R 0xba +#define TEGRA234_MEMORY_CLIENT_NVL2W 0xbb +/* VI FLACON read clients */ +#define TEGRA234_MEMORY_CLIENT_VIFALR 0xbc +/* VIFAL write clients */ +#define TEGRA234_MEMORY_CLIENT_VIFALW 0xbd +/* DLA0ARDA read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe +/* DLA0 Falcon read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf +/* DLA0 write clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0 +/* DLA0 write clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1 +/* DLA1ARDA read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2 +/* DLA1 Falcon read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3 +/* DLA1 write clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4 +/* DLA1 write clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5 +/* PVA0RDA read clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6 +/* PVA0RDB read clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7 +/* PVA0RDC read clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8 +/* PVA0WRA write clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9 +/* PVA0WRB write clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca +/* PVA0WRC write clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb +/* RCE read client */ +#define TEGRA234_MEMORY_CLIENT_RCER 0xd2 +/* RCE write client */ +#define TEGRA234_MEMORY_CLIENT_RCEW 0xd3 +/* RCEDMA read client */ +#define TEGRA234_MEMORY_CLIENT_RCEDMAR 0xd4 +/* RCEDMA write client */ +#define TEGRA234_MEMORY_CLIENT_RCEDMAW 0xd5 /* PCIE0 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 /* PCIE0 write clients */ @@ -137,7 +501,39 @@ #define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 /* PCIE5 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 +/* ISP read client 1 for Crossbar A */ +#define TEGRA234_MEMORY_CLIENT_ISPFALW 0xe4 +#define TEGRA234_MEMORY_CLIENT_NVL3R 0xe5 +#define TEGRA234_MEMORY_CLIENT_NVL3W 0xe6 +#define TEGRA234_MEMORY_CLIENT_NVL4R 0xe7 +#define TEGRA234_MEMORY_CLIENT_NVL4W 0xe8 +/* DLA0ARDA1 read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9 +/* DLA1ARDA1 read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea +/* PVA0RDA1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb +/* PVA0RDB1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec /* PCIE5r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef +#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0 +/* ISP read client for Crossbar A */ +#define TEGRA234_MEMORY_CLIENT_ISPRA1 0xf2 +#define TEGRA234_MEMORY_CLIENT_NVL0RHP 0xf4 +#define TEGRA234_MEMORY_CLIENT_NVL1RHP 0xf5 +#define TEGRA234_MEMORY_CLIENT_NVL2RHP 0xf6 +#define TEGRA234_MEMORY_CLIENT_NVL3RHP 0xf7 +#define TEGRA234_MEMORY_CLIENT_NVL4RHP 0xf8 +/* MSS internal memqual MIU5 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU5R 0xfc +/* MSS internal memqual MIU5 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU5W 0xfd +/* MSS internal memqual MIU6 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU6R 0xfe +/* MSS internal memqual MIU6 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU6W 0xff +#define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123 +#define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124 #endif diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index f5f82dde7399..1e19e258a74d 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -4,6 +4,16 @@ #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H #define _DT_BINDINGS_POWER_QCOM_RPMPD_H +/* SDM670 Power Domain Indexes */ +#define SDM670_MX 0 +#define SDM670_MX_AO 1 +#define SDM670_CX 2 +#define SDM670_CX_AO 3 +#define SDM670_LMX 4 +#define SDM670_LCX 5 +#define SDM670_GFX 6 +#define SDM670_MSS 7 + /* SDM845 Power Domain Indexes */ #define SDM845_EBI 0 #define SDM845_MX 1 @@ -103,6 +113,28 @@ #define SM8450_MXC_AO 11 #define SM8450_MSS 12 +/* SM8550 Power Domain Indexes */ +#define SM8550_CX 0 +#define SM8550_CX_AO 1 +#define SM8550_EBI 2 +#define SM8550_GFX 3 +#define SM8550_LCX 4 +#define SM8550_LMX 5 +#define SM8550_MMCX 6 +#define SM8550_MMCX_AO 7 +#define SM8550_MX 8 +#define SM8550_MX_AO 9 +#define SM8550_MXC 10 +#define SM8550_MXC_AO 11 +#define SM8550_MSS 12 +#define SM8550_NSP 13 + +/* QDU1000/QRU1000 Power Domain Indexes */ +#define QDU1000_EBI 0 +#define QDU1000_MSS 1 +#define QDU1000_CX 2 +#define QDU1000_MX 3 + /* SC7180 Power Domain Indexes */ #define SC7180_CX 0 #define SC7180_CX_AO 1 @@ -274,6 +306,16 @@ #define SDM660_SSCMX 8 #define SDM660_SSCMX_VFL 9 +/* SM4250 Power Domains */ +#define SM4250_VDDCX 0 +#define SM4250_VDDCX_AO 1 +#define SM4250_VDDCX_VFL 2 +#define SM4250_VDDMX 3 +#define SM4250_VDDMX_AO 4 +#define SM4250_VDDMX_VFL 5 +#define SM4250_VDD_LPI_CX 6 +#define SM4250_VDD_LPI_MX 7 + /* SM6115 Power Domains */ #define SM6115_VDDCX 0 #define SM6115_VDDCX_AO 1 diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h index ae9286cef85c..b0fec2ddec84 100644 --- a/include/dt-bindings/power/tegra234-powergate.h +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -4,6 +4,7 @@ #ifndef __ABI_MACH_T234_POWERGATE_T234_H_ #define __ABI_MACH_T234_POWERGATE_T234_H_ +#define TEGRA234_POWER_DOMAIN_OFA 1U #define TEGRA234_POWER_DOMAIN_AUD 2U #define TEGRA234_POWER_DOMAIN_DISP 3U #define TEGRA234_POWER_DOMAIN_PCIEX8A 5U @@ -11,6 +12,9 @@ #define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U #define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U #define TEGRA234_POWER_DOMAIN_PCIEX1A 9U +#define TEGRA234_POWER_DOMAIN_XUSBA 10U +#define TEGRA234_POWER_DOMAIN_XUSBB 11U +#define TEGRA234_POWER_DOMAIN_XUSBC 12U #define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U #define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U #define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U @@ -19,6 +23,17 @@ #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U #define TEGRA234_POWER_DOMAIN_MGBED 20U +#define TEGRA234_POWER_DOMAIN_ISPA 22U +#define TEGRA234_POWER_DOMAIN_NVDEC 23U +#define TEGRA234_POWER_DOMAIN_NVJPGA 24U +#define TEGRA234_POWER_DOMAIN_NVENC 25U +#define TEGRA234_POWER_DOMAIN_VI 28U #define TEGRA234_POWER_DOMAIN_VIC 29U +#define TEGRA234_POWER_DOMAIN_PVA 30U +#define TEGRA234_POWER_DOMAIN_DLAA 32U +#define TEGRA234_POWER_DOMAIN_DLAB 33U +#define TEGRA234_POWER_DOMAIN_CV 34U +#define TEGRA234_POWER_DOMAIN_GPU 35U +#define TEGRA234_POWER_DOMAIN_NVJPGB 36U #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index d48d22b2bc7f..85cc423a7bdf 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -10,14 +10,29 @@ * @brief Identifiers for Resets controllable by firmware * @{ */ +#define TEGRA234_RESET_ACTMON 1U +#define TEGRA234_RESET_ADSP_ALL 2U +#define TEGRA234_RESET_DSI_CORE 3U +#define TEGRA234_RESET_CAN1 4U +#define TEGRA234_RESET_CAN2 5U +#define TEGRA234_RESET_DLA0 6U +#define TEGRA234_RESET_DLA1 7U +#define TEGRA234_RESET_DPAUX 8U +#define TEGRA234_RESET_OFA 9U +#define TEGRA234_RESET_NVJPG1 10U #define TEGRA234_RESET_PEX1_CORE_6 11U #define TEGRA234_RESET_PEX1_CORE_6_APB 12U #define TEGRA234_RESET_PEX1_COMMON_APB 13U #define TEGRA234_RESET_PEX2_CORE_7 14U #define TEGRA234_RESET_PEX2_CORE_7_APB 15U +#define TEGRA234_RESET_NVDISPLAY 16U +#define TEGRA234_RESET_EQOS 17U #define TEGRA234_RESET_GPCDMA 18U +#define TEGRA234_RESET_GPU 19U #define TEGRA234_RESET_HDA 20U #define TEGRA234_RESET_HDACODEC 21U +#define TEGRA234_RESET_EQOS_MACSEC 22U +#define TEGRA234_RESET_EQOS_MACSEC_SECURE 23U #define TEGRA234_RESET_I2C1 24U #define TEGRA234_RESET_PEX2_CORE_8 25U #define TEGRA234_RESET_PEX2_CORE_8_APB 26U @@ -30,15 +45,36 @@ #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_ISP 36U +#define TEGRA234_RESET_MIPI_CAL 37U +#define TEGRA234_RESET_MPHY_CLK_CTL 38U +#define TEGRA234_RESET_MPHY_L0_RX 39U +#define TEGRA234_RESET_MPHY_L0_TX 40U +#define TEGRA234_RESET_MPHY_L1_RX 41U +#define TEGRA234_RESET_MPHY_L1_TX 42U +#define TEGRA234_RESET_NVCSI 43U +#define TEGRA234_RESET_NVDEC 44U #define TEGRA234_RESET_MGBE0_PCS 45U #define TEGRA234_RESET_MGBE0_MAC 46U +#define TEGRA234_RESET_MGBE0_MACSEC 47U +#define TEGRA234_RESET_MGBE0_MACSEC_SECURE 48U #define TEGRA234_RESET_MGBE1_PCS 49U #define TEGRA234_RESET_MGBE1_MAC 50U +#define TEGRA234_RESET_MGBE1_MACSEC 51U +#define TEGRA234_RESET_MGBE1_MACSEC_SECURE 52U #define TEGRA234_RESET_MGBE2_PCS 53U #define TEGRA234_RESET_MGBE2_MAC 54U +#define TEGRA234_RESET_MGBE2_MACSEC 55U #define TEGRA234_RESET_PEX2_CORE_10 56U #define TEGRA234_RESET_PEX2_CORE_10_APB 57U #define TEGRA234_RESET_PEX2_COMMON_APB 58U +#define TEGRA234_RESET_NVENC 59U +#define TEGRA234_RESET_MGBE2_MACSEC_SECURE 60U +#define TEGRA234_RESET_NVJPG 61U +#define TEGRA234_RESET_LA 64U +#define TEGRA234_RESET_HWPM 65U +#define TEGRA234_RESET_PVA0_ALL 66U +#define TEGRA234_RESET_CEC 67U #define TEGRA234_RESET_PWM1 68U #define TEGRA234_RESET_PWM2 69U #define TEGRA234_RESET_PWM3 70U @@ -49,11 +85,43 @@ #define TEGRA234_RESET_PWM8 75U #define TEGRA234_RESET_QSPI0 76U #define TEGRA234_RESET_QSPI1 77U +#define TEGRA234_RESET_I2S7 78U +#define TEGRA234_RESET_I2S8 79U +#define TEGRA234_RESET_SCE_ALL 80U +#define TEGRA234_RESET_RCE_ALL 81U +#define TEGRA234_RESET_SDMMC1 82U +#define TEGRA234_RESET_RSVD_83 83U +#define TEGRA234_RESET_RSVD_84 84U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_MGBE3_PCS 87U #define TEGRA234_RESET_MGBE3_MAC 88U +#define TEGRA234_RESET_MGBE3_MACSEC 89U +#define TEGRA234_RESET_MGBE3_MACSEC_SECURE 90U +#define TEGRA234_RESET_SPI1 91U +#define TEGRA234_RESET_SPI2 92U +#define TEGRA234_RESET_SPI3 93U +#define TEGRA234_RESET_SPI4 94U +#define TEGRA234_RESET_TACH0 95U +#define TEGRA234_RESET_TACH1 96U +#define TEGRA234_RESET_SPI5 97U +#define TEGRA234_RESET_TSEC 98U +#define TEGRA234_RESET_UARTI 99U #define TEGRA234_RESET_UARTA 100U -#define TEGRA234_RESET_VIC 113U +#define TEGRA234_RESET_UARTB 101U +#define TEGRA234_RESET_UARTC 102U +#define TEGRA234_RESET_UARTD 103U +#define TEGRA234_RESET_UARTE 104U +#define TEGRA234_RESET_UARTF 105U +#define TEGRA234_RESET_UARTJ 106U +#define TEGRA234_RESET_UARTH 107U +#define TEGRA234_RESET_UFSHC 108U +#define TEGRA234_RESET_UFSHC_AXI_M 109U +#define TEGRA234_RESET_UFSHC_LP_SEQ 110U +#define TEGRA234_RESET_RSVD_111 111U +#define TEGRA234_RESET_VI 112U +#define TEGRA234_RESET_VIC 113U +#define TEGRA234_RESET_XUSB_PADCTL 114U +#define TEGRA234_RESET_VI2 115U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U #define TEGRA234_RESET_PEX0_CORE_2 118U @@ -65,8 +133,49 @@ #define TEGRA234_RESET_PEX0_CORE_3_APB 124U #define TEGRA234_RESET_PEX0_CORE_4_APB 125U #define TEGRA234_RESET_PEX0_COMMON_APB 126U +#define TEGRA234_RESET_RSVD_127 127U +#define TEGRA234_RESET_NVHS_UPHY_PLL1 128U #define TEGRA234_RESET_PEX1_CORE_5 129U #define TEGRA234_RESET_PEX1_CORE_5_APB 130U +#define TEGRA234_RESET_GBE_UPHY 131U +#define TEGRA234_RESET_GBE_UPHY_PM 132U +#define TEGRA234_RESET_NVHS_UPHY 133U +#define TEGRA234_RESET_NVHS_UPHY_PLL0 134U +#define TEGRA234_RESET_NVHS_UPHY_L0 135U +#define TEGRA234_RESET_NVHS_UPHY_L1 136U +#define TEGRA234_RESET_NVHS_UPHY_L2 137U +#define TEGRA234_RESET_NVHS_UPHY_L3 138U +#define TEGRA234_RESET_NVHS_UPHY_L4 139U +#define TEGRA234_RESET_NVHS_UPHY_L5 140U +#define TEGRA234_RESET_NVHS_UPHY_L6 141U +#define TEGRA234_RESET_NVHS_UPHY_L7 142U +#define TEGRA234_RESET_NVHS_UPHY_PM 143U +#define TEGRA234_RESET_DMIC5 144U +#define TEGRA234_RESET_APE 145U +#define TEGRA234_RESET_PEX_USB_UPHY 146U +#define TEGRA234_RESET_PEX_USB_UPHY_L0 147U +#define TEGRA234_RESET_PEX_USB_UPHY_L1 148U +#define TEGRA234_RESET_PEX_USB_UPHY_L2 149U +#define TEGRA234_RESET_PEX_USB_UPHY_L3 150U +#define TEGRA234_RESET_PEX_USB_UPHY_L4 151U +#define TEGRA234_RESET_PEX_USB_UPHY_L5 152U +#define TEGRA234_RESET_PEX_USB_UPHY_L6 153U +#define TEGRA234_RESET_PEX_USB_UPHY_L7 154U +#define TEGRA234_RESET_PEX_USB_UPHY_PLL0 159U +#define TEGRA234_RESET_PEX_USB_UPHY_PLL1 160U +#define TEGRA234_RESET_PEX_USB_UPHY_PLL2 161U +#define TEGRA234_RESET_PEX_USB_UPHY_PLL3 162U +#define TEGRA234_RESET_GBE_UPHY_L0 163U +#define TEGRA234_RESET_GBE_UPHY_L1 164U +#define TEGRA234_RESET_GBE_UPHY_L2 165U +#define TEGRA234_RESET_GBE_UPHY_L3 166U +#define TEGRA234_RESET_GBE_UPHY_L4 167U +#define TEGRA234_RESET_GBE_UPHY_L5 168U +#define TEGRA234_RESET_GBE_UPHY_L6 169U +#define TEGRA234_RESET_GBE_UPHY_L7 170U +#define TEGRA234_RESET_GBE_UPHY_PLL0 171U +#define TEGRA234_RESET_GBE_UPHY_PLL1 172U +#define TEGRA234_RESET_GBE_UPHY_PLL2 173U /** @} */ diff --git a/include/linux/bcm47xx_nvram.h b/include/linux/bcm47xx_nvram.h index 53b31f69b74a..7615f8d7b1ed 100644 --- a/include/linux/bcm47xx_nvram.h +++ b/include/linux/bcm47xx_nvram.h @@ -11,6 +11,7 @@ #include <linux/vmalloc.h> #ifdef CONFIG_BCM47XX_NVRAM +int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, size_t res_size); int bcm47xx_nvram_init_from_mem(u32 base, u32 lim); int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len); int bcm47xx_nvram_gpio_pin(const char *name); @@ -20,6 +21,11 @@ static inline void bcm47xx_nvram_release_contents(char *nvram) vfree(nvram); }; #else +static inline int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, + size_t res_size) +{ + return -ENOTSUPP; +} static inline int bcm47xx_nvram_init_from_mem(u32 base, u32 lim) { return -ENOTSUPP; diff --git a/include/linux/platform_data/gpmc-omap.h b/include/linux/platform_data/gpmc-omap.h index c9cc4e32435d..dcca6c5e23bb 100644 --- a/include/linux/platform_data/gpmc-omap.h +++ b/include/linux/platform_data/gpmc-omap.h @@ -136,6 +136,13 @@ struct gpmc_device_timings { #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */ #define GPMC_MUX_AD 2 /* Addr-Data multiplex */ +/* Wait pin polarity values */ +#define GPMC_WAITPINPOLARITY_INVALID UINT_MAX +#define GPMC_WAITPINPOLARITY_ACTIVE_LOW 0 +#define GPMC_WAITPINPOLARITY_ACTIVE_HIGH 1 + +#define GPMC_WAITPIN_INVALID UINT_MAX + struct gpmc_settings { bool burst_wrap; /* enables wrap bursting */ bool burst_read; /* enables read page/burst mode */ @@ -149,6 +156,7 @@ struct gpmc_settings { u32 device_width; /* device bus width (8 or 16 bit) */ u32 mux_add_data; /* multiplex address & data */ u32 wait_pin; /* wait-pin to be used */ + u32 wait_pin_polarity; }; /* Data for each chip select */ diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index ebc351698090..1cd41bdf73cf 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -17,6 +17,7 @@ #include <linux/notifier.h> #include <linux/spinlock.h> #include <linux/cpumask.h> +#include <linux/time64.h> /* * Flags to control the behaviour of a genpd. @@ -95,6 +96,7 @@ struct genpd_governor_data { s64 max_off_time_ns; bool max_off_time_changed; ktime_t next_wakeup; + ktime_t next_hrtimer; bool cached_power_down_ok; bool cached_power_down_state_idx; }; @@ -232,6 +234,7 @@ int dev_pm_genpd_set_performance_state(struct device *dev, unsigned int state); int dev_pm_genpd_add_notifier(struct device *dev, struct notifier_block *nb); int dev_pm_genpd_remove_notifier(struct device *dev); void dev_pm_genpd_set_next_wakeup(struct device *dev, ktime_t next); +ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev); extern struct dev_power_governor simple_qos_governor; extern struct dev_power_governor pm_domain_always_on_gov; @@ -293,6 +296,10 @@ static inline int dev_pm_genpd_remove_notifier(struct device *dev) static inline void dev_pm_genpd_set_next_wakeup(struct device *dev, ktime_t next) { } +static inline ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev) +{ + return KTIME_MAX; +} #define simple_qos_governor (*(struct dev_power_governor *)(NULL)) #define pm_domain_always_on_gov (*(struct dev_power_governor *)(NULL)) #endif diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index d2b02bb43768..b85f66db33e1 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -9,6 +9,13 @@ enum mtk_ddp_comp_id; struct device; +enum mtk_dpi_out_format_con { + MTK_DPI_RGB888_SDR_CON, + MTK_DPI_RGB888_DDR_CON, + MTK_DPI_RGB565_SDR_CON, + MTK_DPI_RGB565_DDR_CON +}; + enum mtk_ddp_comp_id { DDP_COMPONENT_AAL0, DDP_COMPONENT_AAL1, diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index bc2fb8343a94..ad1fd718169d 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -42,7 +42,19 @@ #define LLCC_CPUHWT 36 #define LLCC_MDMCLAD2 37 #define LLCC_CAMEXP1 38 +#define LLCC_CMPTHCP 39 +#define LLCC_LCPDARE 40 #define LLCC_AENPU 45 +#define LLCC_ISLAND1 46 +#define LLCC_ISLAND2 47 +#define LLCC_ISLAND3 48 +#define LLCC_ISLAND4 49 +#define LLCC_CAMEXP2 50 +#define LLCC_CAMEXP3 51 +#define LLCC_CAMEXP4 52 +#define LLCC_DISP_WB 53 +#define LLCC_DISP_1 54 +#define LLCC_VIDVSP 64 /** * struct llcc_slice_desc - Cache slice descriptor diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h index 9c0ad64b8d29..862eff613dc7 100644 --- a/include/memory/renesas-rpc-if.h +++ b/include/memory/renesas-rpc-if.h @@ -59,6 +59,7 @@ struct rpcif_op { enum rpcif_type { RPCIF_RCAR_GEN3, + RPCIF_RCAR_GEN4, RPCIF_RZ_G2L, }; diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index b02e9fe69146..eb5079904cc8 100644 --- a/include/soc/fsl/qe/qe.h +++ b/include/soc/fsl/qe/qe.h @@ -172,14 +172,15 @@ static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } /* * Pin multiplexing functions. */ +struct device; struct qe_pin; #ifdef CONFIG_QE_GPIO -extern struct qe_pin *qe_pin_request(struct device_node *np, int index); +extern struct qe_pin *qe_pin_request(struct device *dev, int index); extern void qe_pin_free(struct qe_pin *qe_pin); extern void qe_pin_set_gpio(struct qe_pin *qe_pin); extern void qe_pin_set_dedicated(struct qe_pin *pin); #else -static inline struct qe_pin *qe_pin_request(struct device_node *np, int index) +static inline struct qe_pin *qe_pin_request(struct device *dev, int index) { return ERR_PTR(-ENOSYS); } diff --git a/include/soc/qcom/qcom-spmi-pmic.h b/include/soc/qcom/qcom-spmi-pmic.h index 72398ff44719..c47cc71a999e 100644 --- a/include/soc/qcom/qcom-spmi-pmic.h +++ b/include/soc/qcom/qcom-spmi-pmic.h @@ -26,18 +26,29 @@ #define PM8901_SUBTYPE 0x0f #define PM8950_SUBTYPE 0x10 #define PMI8950_SUBTYPE 0x11 +#define PMK8001_SUBTYPE 0x12 +#define PMI8996_SUBTYPE 0x13 #define PM8998_SUBTYPE 0x14 #define PMI8998_SUBTYPE 0x15 #define PM8005_SUBTYPE 0x18 -#define PM660L_SUBTYPE 0x1A -#define PM660_SUBTYPE 0x1B -#define PM8150_SUBTYPE 0x1E +#define PM660L_SUBTYPE 0x1a +#define PM660_SUBTYPE 0x1b +#define PM8150_SUBTYPE 0x1e #define PM8150L_SUBTYPE 0x1f #define PM8150B_SUBTYPE 0x20 #define PMK8002_SUBTYPE 0x21 #define PM8009_SUBTYPE 0x24 +#define PMI632_SUBTYPE 0x25 #define PM8150C_SUBTYPE 0x26 +#define PM6150_SUBTYPE 0x28 #define SMB2351_SUBTYPE 0x29 +#define PM8008_SUBTYPE 0x2c +#define PM6125_SUBTYPE 0x2d +#define PM7250B_SUBTYPE 0x2e +#define PMK8350_SUBTYPE 0x2f +#define PMR735B_SUBTYPE 0x34 +#define PM6350_SUBTYPE 0x36 +#define PM2250_SUBTYPE 0x37 #define PMI8998_FAB_ID_SMIC 0x11 #define PMI8998_FAB_ID_GF 0x30 diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h index 53171e324d1c..ecefcaec7e66 100644 --- a/include/soc/tegra/bpmp-abi.h +++ b/include/soc/tegra/bpmp-abi.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef ABI_BPMP_ABI_H @@ -74,6 +74,32 @@ /** * @ingroup MRQ_Format + * Request an answer from the peer. + * This should be set in mrq_request::flags for all requests targetted + * at BPMP. For requests originating in BPMP, this flag is optional except + * for messages targeting MCE, for which the field must be set. + * When this flag is not set, the remote peer must not send a response + * back. + */ +#define BPMP_MAIL_DO_ACK (1U << 0U) + +/** + * @ingroup MRQ_Format + * Ring the sender's doorbell when responding. This should be set unless + * the sender wants to poll the underlying communications layer directly. + * + * An optional direction that can be specified in mrq_request::flags. + */ +#define BPMP_MAIL_RING_DB (1U << 1U) + +/** + * @ingroup MRQ_Format + * CRC present + */ +#define BPMP_MAIL_CRC_PRESENT (1U << 2U) + +/** + * @ingroup MRQ_Format * @brief Header for an MRQ message * * Provides the MRQ number for the MRQ message: #mrq. The remainder of @@ -85,12 +111,139 @@ struct mrq_request { uint32_t mrq; /** - * @brief Flags providing follow up directions to the receiver + * @brief 32bit word containing a number of fields as follows: + * + * struct { + * uint8_t options:4; + * uint8_t xid:4; + * uint8_t payload_length; + * uint16_t crc16; + * }; + * + * **options** directions to the receiver and indicates CRC presence. + * + * #BPMP_MAIL_DO_ACK and #BPMP_MAIL_RING_DB see documentation of respective options. + * #BPMP_MAIL_CRC_PRESENT is supported on T234 and later platforms. It indicates the + * crc16, xid and length fields are present when set. + * Some platform configurations, especially when targeted to applications requiring + * functional safety, mandate this option being set or otherwise will respond with + * -BPMP_EBADMSG and ignore the request. + * + * **xid** is a transaction ID. + * + * Only used when #BPMP_MAIL_CRC_PRESENT is set. + * + * **payload_length** of the message expressed in bytes without the size of this header. + * See table below for minimum accepted payload lengths for each MRQ. + * Note: For DMCE communication, this field expresses the length as a multiple of 4 bytes + * rather than bytes. + * + * Only used when #BPMP_MAIL_CRC_PRESENT is set. + * + * | MRQ | CMD | minimum payload length + * | -------------------- | ------------------------------------ | ------------------------------------------ | + * | MRQ_PING | | 4 | + * | MRQ_THREADED_PING | | 4 | + * | MRQ_RESET | any | 8 | + * | MRQ_I2C | | 12 + cmd_i2c_xfer_request.data_size | + * | MRQ_CLK | CMD_CLK_GET_RATE | 4 | + * | MRQ_CLK | CMD_CLK_SET_RATE | 16 | + * | MRQ_CLK | CMD_CLK_ROUND_RATE | 16 | + * | MRQ_CLK | CMD_CLK_GET_PARENT | 4 | + * | MRQ_CLK | CMD_CLK_SET_PARENT | 8 | + * | MRQ_CLK | CMD_CLK_ENABLE | 4 | + * | MRQ_CLK | CMD_CLK_DISABLE | 4 | + * | MRQ_CLK | CMD_CLK_IS_ENABLED | 4 | + * | MRQ_CLK | CMD_CLK_GET_ALL_INFO | 4 | + * | MRQ_CLK | CMD_CLK_GET_MAX_CLK_ID | 4 | + * | MRQ_CLK | CMD_CLK_GET_FMAX_AT_VMIN | 4 | + * | MRQ_QUERY_ABI | | 4 | + * | MRQ_PG | CMD_PG_QUERY_ABI | 12 | + * | MRQ_PG | CMD_PG_SET_STATE | 12 | + * | MRQ_PG | CMD_PG_GET_STATE | 8 | + * | MRQ_PG | CMD_PG_GET_NAME | 8 | + * | MRQ_PG | CMD_PG_GET_MAX_ID | 8 | + * | MRQ_THERMAL | CMD_THERMAL_QUERY_ABI | 8 | + * | MRQ_THERMAL | CMD_THERMAL_GET_TEMP | 8 | + * | MRQ_THERMAL | CMD_THERMAL_SET_TRIP | 20 | + * | MRQ_THERMAL | CMD_THERMAL_GET_NUM_ZONES | 4 | + * | MRQ_THERMAL | CMD_THERMAL_GET_THERMTRIP | 8 | + * | MRQ_CPU_VHINT | | 8 | + * | MRQ_ABI_RATCHET | | 2 | + * | MRQ_EMC_DVFS_LATENCY | | 8 | + * | MRQ_EMC_DVFS_EMCHUB | | 8 | + * | MRQ_EMC_DISP_RFL | | 4 | + * | MRQ_BWMGR | CMD_BWMGR_QUERY_ABI | 8 | + * | MRQ_BWMGR | CMD_BWMGR_CALC_RATE | 8 + 8 * bwmgr_rate_req.num_iso_clients | + * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_QUERY_ABI | 8 | + * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_CALCULATE_LA | 16 | + * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_SET_LA | 16 | + * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_GET_MAX_BW | 8 | + * | MRQ_CPU_NDIV_LIMITS | | 4 | + * | MRQ_CPU_AUTO_CC3 | | 4 | + * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_QUERY_ABI | 8 | + * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_READ | 5 | + * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_WRITE | 5 + cmd_ringbuf_console_write_req.len | + * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_GET_FIFO | 4 | + * | MRQ_STRAP | STRAP_SET | 12 | + * | MRQ_UPHY | CMD_UPHY_PCIE_LANE_MARGIN_CONTROL | 24 | + * | MRQ_UPHY | CMD_UPHY_PCIE_LANE_MARGIN_STATUS | 4 | + * | MRQ_UPHY | CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT | 5 | + * | MRQ_UPHY | CMD_UPHY_PCIE_CONTROLLER_STATE | 6 | + * | MRQ_UPHY | CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF | 5 | + * | MRQ_FMON | CMD_FMON_GEAR_CLAMP | 16 | + * | MRQ_FMON | CMD_FMON_GEAR_FREE | 4 | + * | MRQ_FMON | CMD_FMON_GEAR_GET | 4 | + * | MRQ_FMON | CMD_FMON_FAULT_STS_GET | 8 | + * | MRQ_EC | CMD_EC_STATUS_EX_GET | 12 | + * | MRQ_QUERY_FW_TAG | | 0 | + * | MRQ_DEBUG | CMD_DEBUG_OPEN_RO | 4 + length of cmd_debug_fopen_request.name | + * | MRQ_DEBUG | CMD_DEBUG_OPEN_WO | 4 + length of cmd_debug_fopen_request.name | + * | MRQ_DEBUG | CMD_DEBUG_READ | 8 | + * | MRQ_DEBUG | CMD_DEBUG_WRITE | 12 + cmd_debug_fwrite_request.datalen | + * | MRQ_DEBUG | CMD_DEBUG_CLOSE | 8 | + * | MRQ_TELEMETRY | | 8 | + * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_QUERY_ABI | 8 | + * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_SET | 20 | + * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_GET | 16 | + * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_CURR_CAP | 8 | + * | MRQ_GEARS | | 0 | + * | MRQ_BWMGR_INT | CMD_BWMGR_INT_QUERY_ABI | 8 | + * | MRQ_BWMGR_INT | CMD_BWMGR_INT_CALC_AND_SET | 16 | + * | MRQ_BWMGR_INT | CMD_BWMGR_INT_CAP_SET | 8 | + * | MRQ_OC_STATUS | | 0 | + * + * **crc16** + * + * CRC16 using polynomial x^16 + x^14 + x^12 + x^11 + x^8 + x^5 + x^4 + x^2 + 1 + * and initialization value 0x4657. The CRC is calculated over all bytes of the message + * including this header. However the crc16 field is considered to be set to 0 when + * calculating the CRC. Only used when #BPMP_MAIL_CRC_PRESENT is set. If + * #BPMP_MAIL_CRC_PRESENT is set and this field does not match the CRC as + * calculated by BPMP, -BPMP_EBADMSG will be returned and the request will + * be ignored. See code snippet below on how to calculate the CRC. * - * | Bit | Description | - * |-----|--------------------------------------------| - * | 1 | ring the sender's doorbell when responding | - * | 0 | should be 1 | + * @code + * uint16_t calc_crc_digest(uint16_t crc, uint8_t *data, size_t size) + * { + * for (size_t i = 0; i < size; i++) { + * crc ^= data[i] << 8; + * for (size_t j = 0; j < 8; j++) { + * if ((crc & 0x8000) == 0x8000) { + * crc = (crc << 1) ^ 0xAC9A; + * } else { + * crc = (crc << 1); + * } + * } + * } + * return crc; + * } + * + * uint16_t calc_crc(uint8_t *data, size_t size) + * { + * return calc_crc_digest(0x4657, data, size); + * } + * @endcode */ uint32_t flags; } BPMP_ABI_PACKED; @@ -107,7 +260,35 @@ struct mrq_request { struct mrq_response { /** @brief Error code for the MRQ request itself */ int32_t err; - /** @brief Reserved for future use */ + + /** + * @brief 32bit word containing a number of fields as follows: + * + * struct { + * uint8_t options:4; + * uint8_t xid:4; + * uint8_t payload_length; + * uint16_t crc16; + * }; + * + * **options** indicates CRC presence. + * + * #BPMP_MAIL_CRC_PRESENT is supported on T234 and later platforms and + * indicates the crc16 related fields are present when set. + * + * **xid** is the transaction ID as sent by the requestor. + * + * **length** of the message expressed in bytes without the size of this header. + * Note: For DMCE communication, this field expresses the length as a multiple of 4 bytes + * rather than bytes. + * + * **crc16** + * + * CRC16 using polynomial x^16 + x^14 + x^12 + x^11 + x^8 + x^5 + x^4 + x^2 + 1 + * and initialization value 0x4657. The CRC is calculated over all bytes of the message + * including this header. However the crc16 field is considered to be set to 0 when + * calculating the CRC. Only used when #BPMP_MAIL_CRC_PRESENT is set. + */ uint32_t flags; } BPMP_ABI_PACKED; @@ -131,24 +312,16 @@ struct mrq_response { #define MRQ_PING 0U #define MRQ_QUERY_TAG 1U -#define MRQ_MODULE_LOAD 4U -#define MRQ_MODULE_UNLOAD 5U -#define MRQ_TRACE_MODIFY 7U -#define MRQ_WRITE_TRACE 8U #define MRQ_THREADED_PING 9U -#define MRQ_MODULE_MAIL 11U #define MRQ_DEBUGFS 19U #define MRQ_RESET 20U #define MRQ_I2C 21U #define MRQ_CLK 22U #define MRQ_QUERY_ABI 23U -#define MRQ_PG_READ_STATE 25U -#define MRQ_PG_UPDATE_STATE 26U #define MRQ_THERMAL 27U #define MRQ_CPU_VHINT 28U #define MRQ_ABI_RATCHET 29U #define MRQ_EMC_DVFS_LATENCY 31U -#define MRQ_TRACE_ITER 64U #define MRQ_RINGBUF_CONSOLE 65U #define MRQ_PG 66U #define MRQ_CPU_NDIV_LIMITS 67U @@ -159,6 +332,40 @@ struct mrq_response { #define MRQ_FMON 72U #define MRQ_EC 73U #define MRQ_DEBUG 75U +#define MRQ_EMC_DVFS_EMCHUB 76U +#define MRQ_BWMGR 77U +#define MRQ_ISO_CLIENT 78U +#define MRQ_EMC_DISP_RFL 79U +#define MRQ_TELEMETRY 80U +#define MRQ_PWR_LIMIT 81U +#define MRQ_GEARS 82U +#define MRQ_BWMGR_INT 83U +#define MRQ_OC_STATUS 84U + +/** @cond DEPRECATED */ +#define MRQ_RESERVED_2 2U +#define MRQ_RESERVED_3 3U +#define MRQ_RESERVED_4 4U +#define MRQ_RESERVED_5 5U +#define MRQ_RESERVED_6 6U +#define MRQ_RESERVED_7 7U +#define MRQ_RESERVED_8 8U +#define MRQ_RESERVED_10 10U +#define MRQ_RESERVED_11 11U +#define MRQ_RESERVED_12 12U +#define MRQ_RESERVED_13 13U +#define MRQ_RESERVED_14 14U +#define MRQ_RESERVED_15 15U +#define MRQ_RESERVED_16 16U +#define MRQ_RESERVED_17 17U +#define MRQ_RESERVED_18 18U +#define MRQ_RESERVED_24 24U +#define MRQ_RESERVED_25 25U +#define MRQ_RESERVED_26 26U +#define MRQ_RESERVED_30 30U +#define MRQ_RESERVED_64 64U +#define MRQ_RESERVED_74 74U +/** @endcond DEPRECATED */ /** @} */ @@ -167,7 +374,7 @@ struct mrq_response { * @brief Maximum MRQ code to be sent by CPU software to * BPMP. Subject to change in future */ -#define MAX_CPU_MRQ_ID 75U +#define MAX_CPU_MRQ_ID 84U /** * @addtogroup MRQ_Payloads @@ -183,8 +390,11 @@ struct mrq_response { * @defgroup ABI_info ABI Info * @defgroup Powergating Power Gating * @defgroup Thermal Thermal + * @defgroup OC_status OC status * @defgroup Vhint CPU Voltage hint * @defgroup EMC EMC + * @defgroup BWMGR BWMGR + * @defgroup ISO_CLIENT ISO_CLIENT * @defgroup CPU NDIV Limits * @defgroup RingbufConsole Ring Buffer Console * @defgroup Strap Straps @@ -192,8 +402,11 @@ struct mrq_response { * @defgroup CC3 Auto-CC3 * @defgroup FMON FMON * @defgroup EC EC - * @defgroup Fbvolt_status Fuse Burn Voltage Status - * @} + * @defgroup Telemetry Telemetry + * @defgroup Pwrlimit PWR_LIMIT + * @defgroup Gears Gears + * @defgroup BWMGR_INT Bandwidth Manager Integrated + * @} MRQ_Payloads */ /** @@ -304,190 +517,6 @@ struct mrq_query_fw_tag_response { uint8_t tag[32]; } BPMP_ABI_PACKED; -/** - * @ingroup MRQ_Codes - * @def MRQ_MODULE_LOAD - * @brief Dynamically load a BPMP code module - * - * * Platforms: T210, T210B01, T186 - * @cond (bpmp_t210 || bpmp_t210b01 || bpmp_t186) - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_module_load_request - * * Response Payload: @ref mrq_module_load_response - * - * @note This MRQ is disabled on production systems - * - */ - -/** - * @ingroup Module - * @brief Request with #MRQ_MODULE_LOAD - * - * Used by #MRQ_MODULE_LOAD calls to ask the recipient to dynamically - * load the code located at #phys_addr and having size #size - * bytes. #phys_addr is treated as a void pointer. - * - * The recipient copies the code from #phys_addr to locally allocated - * memory prior to responding to this message. - * - * @todo document the module header format - * - * The sender is responsible for ensuring that the code is mapped in - * the recipient's address map. - * - */ -struct mrq_module_load_request { - /** @brief Base address of the code to load */ - uint32_t phys_addr; - /** @brief Size in bytes of code to load */ - uint32_t size; -} BPMP_ABI_PACKED; - -/** - * @ingroup Module - * @brief Response to #MRQ_MODULE_LOAD - * - * @todo document mrq_response::err - */ -struct mrq_module_load_response { - /** @brief Handle to the loaded module */ - uint32_t base; -} BPMP_ABI_PACKED; -/** @endcond*/ - -/** - * @ingroup MRQ_Codes - * @def MRQ_MODULE_UNLOAD - * @brief Unload a previously loaded code module - * - * * Platforms: T210, T210B01, T186 - * @cond (bpmp_t210 || bpmp_t210b01 || bpmp_t186) - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_module_unload_request - * * Response Payload: N/A - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Module - * @brief Request with #MRQ_MODULE_UNLOAD - * - * Used by #MRQ_MODULE_UNLOAD calls to request that a previously loaded - * module be unloaded. - */ -struct mrq_module_unload_request { - /** @brief Handle of the module to unload */ - uint32_t base; -} BPMP_ABI_PACKED; -/** @endcond*/ - -/** - * @ingroup MRQ_Codes - * @def MRQ_TRACE_MODIFY - * @brief Modify the set of enabled trace events - * - * @deprecated - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_trace_modify_request - * * Response Payload: @ref mrq_trace_modify_response - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Trace - * @brief Request with #MRQ_TRACE_MODIFY - * - * Used by %MRQ_TRACE_MODIFY calls to enable or disable specify trace - * events. #set takes precedence for any bit set in both #set and - * #clr. - */ -struct mrq_trace_modify_request { - /** @brief Bit mask of trace events to disable */ - uint32_t clr; - /** @brief Bit mask of trace events to enable */ - uint32_t set; -} BPMP_ABI_PACKED; - -/** - * @ingroup Trace - * @brief Response to #MRQ_TRACE_MODIFY - * - * Sent in repsonse to an #MRQ_TRACE_MODIFY message. #mask reflects the - * state of which events are enabled after the recipient acted on the - * message. - * - */ -struct mrq_trace_modify_response { - /** @brief Bit mask of trace event enable states */ - uint32_t mask; -} BPMP_ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_WRITE_TRACE - * @brief Write trace data to a buffer - * - * @deprecated - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_write_trace_request - * * Response Payload: @ref mrq_write_trace_response - * - * mrq_response::err depends on the @ref mrq_write_trace_request field - * values. err is -#BPMP_EINVAL if size is zero or area is NULL or - * area is in an illegal range. A positive value for err indicates the - * number of bytes written to area. - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Trace - * @brief Request with #MRQ_WRITE_TRACE - * - * Used by MRQ_WRITE_TRACE calls to ask the recipient to copy trace - * data from the recipient's local buffer to the output buffer. #area - * is treated as a byte-aligned pointer in the recipient's address - * space. - * - * The sender is responsible for ensuring that the output - * buffer is mapped in the recipient's address map. The recipient is - * responsible for protecting its own code and data from accidental - * overwrites. - */ -struct mrq_write_trace_request { - /** @brief Base address of output buffer */ - uint32_t area; - /** @brief Size in bytes of the output buffer */ - uint32_t size; -} BPMP_ABI_PACKED; - -/** - * @ingroup Trace - * @brief Response to #MRQ_WRITE_TRACE - * - * Once this response is sent, the respondent will not access the - * output buffer further. - */ -struct mrq_write_trace_response { - /** - * @brief Flag whether more data remains in local buffer - * - * Value is 1 if the entire local trace buffer has been - * drained to the outputbuffer. Value is 0 otherwise. - */ - uint32_t eof; -} BPMP_ABI_PACKED; - /** @private */ struct mrq_threaded_ping_request { uint32_t challenge; @@ -500,50 +529,6 @@ struct mrq_threaded_ping_response { /** * @ingroup MRQ_Codes - * @def MRQ_MODULE_MAIL - * @brief Send a message to a loadable module - * - * * Platforms: T210, T210B01, T186 - * @cond (bpmp_t210 || bpmp_t210b01 || bpmp_t186) - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_module_mail_request - * * Response Payload: @ref mrq_module_mail_response - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Module - * @brief Request with #MRQ_MODULE_MAIL - */ -struct mrq_module_mail_request { - /** @brief Handle to the previously loaded module */ - uint32_t base; - /** @brief Module-specific mail payload - * - * The length of data[ ] is unknown to the BPMP core firmware - * but it is limited to the size of an IPC message. - */ - uint8_t data[BPMP_ABI_EMPTY_ARRAY]; -} BPMP_ABI_PACKED; - -/** - * @ingroup Module - * @brief Response to #MRQ_MODULE_MAIL - */ -struct mrq_module_mail_response { - /** @brief Module-specific mail payload - * - * The length of data[ ] is unknown to the BPMP core firmware - * but it is limited to the size of an IPC message. - */ - uint8_t data[BPMP_ABI_EMPTY_ARRAY]; -} BPMP_ABI_PACKED; -/** @endcond */ - -/** - * @ingroup MRQ_Codes * @def MRQ_DEBUGFS * @brief Interact with BPMP's debugfs file nodes * @@ -686,7 +671,7 @@ struct mrq_debugfs_response { #define DEBUGFS_S_ISDIR (1 << 9) #define DEBUGFS_S_IRUSR (1 << 8) #define DEBUGFS_S_IWUSR (1 << 7) -/** @} */ +/** @} Debugfs */ /** * @ingroup MRQ_Codes @@ -931,7 +916,7 @@ enum mrq_reset_commands { * @brief Request with MRQ_RESET * * Used by the sender of an #MRQ_RESET message to request BPMP to - * assert or deassert a given reset line. + * assert or or deassert a given reset line. */ struct mrq_reset_request { /** @brief Reset action to perform (@ref mrq_reset_commands) */ @@ -970,7 +955,7 @@ struct mrq_reset_response { } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ +/** @} Reset */ /** * @ingroup MRQ_Codes @@ -1032,7 +1017,17 @@ struct serial_i2c_request { * @brief Trigger one or more i2c transactions */ struct cmd_i2c_xfer_request { - /** @brief Valid bus number from @ref bpmp_i2c_ids*/ + /** + * @brief Tegra PWR_I2C bus identifier + * + * @cond (bpmp_t234 || bpmp_t239 || bpmp_t194) + * Must be set to 5. + * @endcond (bpmp_t234 || bpmp_t239 || bpmp_t194) + * @cond bpmp_th500 + * Must be set to 1. + * @endcond bpmp_th500 + * + */ uint32_t bus_id; /** @brief Count of valid bytes in #data_buf*/ @@ -1084,7 +1079,7 @@ struct mrq_i2c_response { struct cmd_i2c_xfer_response xfer; } BPMP_ABI_PACKED; -/** @} */ +/** @} I2C */ /** * @ingroup MRQ_Codes @@ -1109,6 +1104,13 @@ enum { CMD_CLK_IS_ENABLED = 6, CMD_CLK_ENABLE = 7, CMD_CLK_DISABLE = 8, +/** @cond DEPRECATED */ + CMD_CLK_PROPERTIES = 9, + CMD_CLK_POSSIBLE_PARENTS = 10, + CMD_CLK_NUM_POSSIBLE_PARENTS = 11, + CMD_CLK_GET_POSSIBLE_PARENT = 12, + CMD_CLK_RESET_REFCOUNTS = 13, +/** @endcond DEPRECATED */ CMD_CLK_GET_ALL_INFO = 14, CMD_CLK_GET_MAX_CLK_ID = 15, CMD_CLK_GET_FMAX_AT_VMIN = 16, @@ -1119,6 +1121,21 @@ enum { #define BPMP_CLK_HAS_SET_RATE (1U << 1U) #define BPMP_CLK_IS_ROOT (1U << 2U) #define BPMP_CLK_IS_VAR_ROOT (1U << 3U) +/** + * @brief Protection against rate and parent changes + * + * #MRQ_CLK command #CMD_CLK_SET_RATE or #MRQ_CLK command #CMD_CLK_SET_PARENT will return + * -#BPMP_EACCES. + */ +#define BPMP_CLK_RATE_PARENT_CHANGE_DENIED (1U << 30) + +/** + * @brief Protection against state changes + * + * #MRQ_CLK command #CMD_CLK_ENABLE or #MRQ_CLK command #CMD_CLK_DISABLE will return + * -#BPMP_EACCES. + */ +#define BPMP_CLK_STATE_CHANGE_DENIED (1U << 31) #define MRQ_CLK_NAME_MAXLEN 40U #define MRQ_CLK_MAX_PARENTS 16U @@ -1210,6 +1227,46 @@ struct cmd_clk_disable_response { BPMP_ABI_EMPTY } BPMP_ABI_PACKED; +/** @cond DEPRECATED */ +/** @private */ +struct cmd_clk_properties_request { + BPMP_ABI_EMPTY +} BPMP_ABI_PACKED; + +/** @todo flags need to be spelled out here */ +struct cmd_clk_properties_response { + uint32_t flags; +} BPMP_ABI_PACKED; + +/** @private */ +struct cmd_clk_possible_parents_request { + BPMP_ABI_EMPTY +} BPMP_ABI_PACKED; + +struct cmd_clk_possible_parents_response { + uint8_t num_parents; + uint8_t reserved[3]; + uint32_t parent_id[MRQ_CLK_MAX_PARENTS]; +} BPMP_ABI_PACKED; + +/** @private */ +struct cmd_clk_num_possible_parents_request { + BPMP_ABI_EMPTY +} BPMP_ABI_PACKED; + +struct cmd_clk_num_possible_parents_response { + uint8_t num_parents; +} BPMP_ABI_PACKED; + +struct cmd_clk_get_possible_parent_request { + uint8_t parent_idx; +} BPMP_ABI_PACKED; + +struct cmd_clk_get_possible_parent_response { + uint32_t parent_id; +} BPMP_ABI_PACKED; +/** @endcond DEPRECATED */ + /** @private */ struct cmd_clk_get_all_info_request { BPMP_ABI_EMPTY @@ -1241,6 +1298,7 @@ struct cmd_clk_get_fmax_at_vmin_response { int64_t rate; } BPMP_ABI_PACKED; + /** * @ingroup Clocks * @brief Request with #MRQ_CLK @@ -1267,6 +1325,17 @@ struct cmd_clk_get_fmax_at_vmin_response { * */ +/** @cond DEPRECATED + * + * Older versions of firmware also supported following sub-commands: + * |CMD_CLK_PROPERTIES |- | + * |CMD_CLK_POSSIBLE_PARENTS |- | + * |CMD_CLK_NUM_POSSIBLE_PARENTS|- | + * |CMD_CLK_GET_POSSIBLE_PARENT |clk_get_possible_parent| + * |CMD_CLK_RESET_REFCOUNTS |- | + * + * @endcond DEPRECATED */ + struct mrq_clk_request { /** @brief Sub-command and clock id concatenated to 32-bit word. * - bits[31..24] is the sub-cmd. @@ -1288,6 +1357,15 @@ struct mrq_clk_request { struct cmd_clk_disable_request clk_disable; /** @private */ struct cmd_clk_is_enabled_request clk_is_enabled; + /** @cond DEPRECATED */ + /** @private */ + struct cmd_clk_properties_request clk_properties; + /** @private */ + struct cmd_clk_possible_parents_request clk_possible_parents; + /** @private */ + struct cmd_clk_num_possible_parents_request clk_num_possible_parents; + struct cmd_clk_get_possible_parent_request clk_get_possible_parent; + /** @endcond DEPRECATED */ /** @private */ struct cmd_clk_get_all_info_request clk_get_all_info; /** @private */ @@ -1321,6 +1399,17 @@ struct mrq_clk_request { * */ +/** @cond DEPRECATED + * + * Older versions of firmware also supported following sub-commands: + * |CMD_CLK_PROPERTIES |clk_properties | + * |CMD_CLK_POSSIBLE_PARENTS |clk_possible_parents | + * |CMD_CLK_NUM_POSSIBLE_PARENTS|clk_num_possible_parents| + * |CMD_CLK_GET_POSSIBLE_PARENT |clk_get_possible_parents| + * |CMD_CLK_RESET_REFCOUNTS |- | + * + * @endcond DEPRECATED */ + struct mrq_clk_response { union { struct cmd_clk_get_rate_response clk_get_rate; @@ -1333,13 +1422,19 @@ struct mrq_clk_response { /** @private */ struct cmd_clk_disable_response clk_disable; struct cmd_clk_is_enabled_response clk_is_enabled; + /** @cond DEPRECATED */ + struct cmd_clk_properties_response clk_properties; + struct cmd_clk_possible_parents_response clk_possible_parents; + struct cmd_clk_num_possible_parents_response clk_num_possible_parents; + struct cmd_clk_get_possible_parent_response clk_get_possible_parent; + /** @endcond DEPRECATED */ struct cmd_clk_get_all_info_response clk_get_all_info; struct cmd_clk_get_max_clk_id_response clk_get_max_clk_id; struct cmd_clk_get_fmax_at_vmin_response clk_get_fmax_at_vmin; } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ +/** @} Clocks */ /** * @ingroup MRQ_Codes @@ -1378,107 +1473,20 @@ struct mrq_query_abi_response { } BPMP_ABI_PACKED; /** - * @ingroup MRQ_Codes - * @def MRQ_PG_READ_STATE - * @brief Read the power-gating state of a partition * - * * Platforms: T186 - * @cond bpmp_t186 - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_pg_read_state_request - * * Response Payload: @ref mrq_pg_read_state_response - */ - -/** - * @ingroup Powergating - * @brief Request with #MRQ_PG_READ_STATE - * - * Used by MRQ_PG_READ_STATE call to read the current state of a - * partition. - */ -struct mrq_pg_read_state_request { - /** @brief ID of partition */ - uint32_t partition_id; -} BPMP_ABI_PACKED; - -/** - * @ingroup Powergating - * @brief Response to MRQ_PG_READ_STATE - * @todo define possible errors. - */ -struct mrq_pg_read_state_response { - /** @brief Read as don't care */ - uint32_t sram_state; - /** @brief State of power partition - * * 0 : off - * * 1 : on - */ - uint32_t logic_state; -} BPMP_ABI_PACKED; -/** @endcond*/ -/** @} */ - -/** - * @ingroup MRQ_Codes - * @def MRQ_PG_UPDATE_STATE - * @brief Modify the power-gating state of a partition. In contrast to - * MRQ_PG calls, the operations that change state (on/off) of power - * partition are reference counted. - * - * * Platforms: T186 - * @cond bpmp_t186 - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_pg_update_state_request - * * Response Payload: N/A - */ - -/** - * @ingroup Powergating - * @brief Request with mrq_pg_update_state_request - * - * Used by #MRQ_PG_UPDATE_STATE call to request BPMP to change the - * state of a power partition #partition_id. - */ -struct mrq_pg_update_state_request { - /** @brief ID of partition */ - uint32_t partition_id; - /** @brief Secondary control of power partition - * @details Ignored by many versions of the BPMP - * firmware. For maximum compatibility, set the value - * according to @ref logic_state - * * 0x1: power ON partition (@ref logic_state == 0x3) - * * 0x3: power OFF partition (@ref logic_state == 0x1) - */ - uint32_t sram_state; - /** @brief Controls state of power partition, legal values are - * * 0x1 : power OFF partition - * * 0x3 : power ON partition - */ - uint32_t logic_state; - /** @brief Change state of clocks of the power partition, legal values - * * 0x0 : do not change clock state - * * 0x1 : disable partition clocks (only applicable when - * @ref logic_state == 0x1) - * * 0x3 : enable partition clocks (only applicable when - * @ref logic_state == 0x3) - */ - uint32_t clock_state; -} BPMP_ABI_PACKED; -/** @endcond*/ - -/** * @ingroup MRQ_Codes * @def MRQ_PG * @brief Control power-gating state of a partition. In contrast to * MRQ_PG_UPDATE_STATE, operations that change the power partition * state are NOT reference counted * - * @note BPMP-FW forcefully turns off some partitions as part of SC7 entry - * because their state cannot be adequately restored on exit. Therefore, - * it is recommended to power off all domains via MRQ_PG prior to SC7 entry. + * @cond (bpmp_t194 || bpmp_t186) + * @note On T194 and earlier BPMP-FW forcefully turns off some partitions as + * part of SC7 entry because their state cannot be adequately restored on exit. + * Therefore, it is recommended to power off all domains via MRQ_PG prior to SC7 + * entry. * See @ref bpmp_pdomain_ids for further detail. + * @endcond (bpmp_t194 || bpmp_t186) * * * Platforms: T186, T194 * * Initiators: Any @@ -1643,7 +1651,7 @@ struct mrq_pg_response { } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ +/** @} Powergating */ /** * @ingroup MRQ_Codes @@ -1889,7 +1897,44 @@ union mrq_thermal_bpmp_to_host_response { struct cmd_thermal_get_thermtrip_response get_thermtrip; struct cmd_thermal_get_num_zones_response get_num_zones; } BPMP_ABI_PACKED; -/** @} */ + +/** @} Thermal */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_OC_STATUS + * @brief Query over current status + * + * * Platforms: T234 + * @cond bpmp_t234 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_oc_status_response + * + * @addtogroup OC_status + * @{ + */ + +#define OC_STATUS_MAX_SIZE 24U + +/* + * @brief Response to #MRQ_OC_STATUS + * + * throt_en: Value for each OC alarm where zero signifies throttle is + * disabled, and non-zero throttle is enabled. + * event_cnt: Total number of OC events for each OC alarm. + * + * mrq_response::err is 0 if the operation was successful and + * -#BPMP_ENODEV otherwise. + */ +struct mrq_oc_status_response { + uint8_t throt_en[OC_STATUS_MAX_SIZE]; + uint32_t event_cnt[OC_STATUS_MAX_SIZE]; +} BPMP_ABI_PACKED; + +/** @} OC_status */ +/** @endcond bpmp_t234 */ /** * @ingroup MRQ_Codes @@ -1948,8 +1993,9 @@ struct cpu_vhint_data { /** reserved for future use */ uint16_t reserved[328]; } BPMP_ABI_PACKED; -/** @endcond */ -/** @} */ + +/** @} Vhint */ +/** @endcond bpmp_t186 */ /** * @ingroup MRQ_Codes @@ -2016,14 +2062,15 @@ struct mrq_abi_ratchet_response { /** @brief BPMP's ratchet value */ uint16_t ratchet; }; -/** @} */ + +/** @} ABI_info */ /** * @ingroup MRQ_Codes * @def MRQ_EMC_DVFS_LATENCY * @brief Query frequency dependent EMC DVFS latency * - * * Platforms: T186, T194 + * * Platforms: T186, T194, T234 * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: N/A @@ -2053,7 +2100,543 @@ struct mrq_emc_dvfs_latency_response { struct emc_dvfs_latency pairs[EMC_DVFS_LATENCY_MAX_SIZE]; } BPMP_ABI_PACKED; -/** @} */ +/** @} EMC */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_EMC_DVFS_EMCHUB + * @brief Query EMC HUB frequencies + * + * * Platforms: T234 onwards + * @cond (bpmp_t234 || bpmp_t239 || bpmp_th500) + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_emc_dvfs_emchub_response + * @addtogroup EMC + * @{ + */ + +/** + * @brief Used by @ref mrq_emc_dvfs_emchub_response + */ +struct emc_dvfs_emchub { + /** @brief EMC DVFS node frequency in kHz */ + uint32_t freq; + /** @brief EMC HUB frequency in kHz */ + uint32_t hub_freq; +} BPMP_ABI_PACKED; + +#define EMC_DVFS_EMCHUB_MAX_SIZE EMC_DVFS_LATENCY_MAX_SIZE +/** + * @brief Response to #MRQ_EMC_DVFS_EMCHUB + */ +struct mrq_emc_dvfs_emchub_response { + /** @brief The number valid entries in #pairs */ + uint32_t num_pairs; + /** @brief EMC DVFS node <frequency, hub frequency> information */ + struct emc_dvfs_emchub pairs[EMC_DVFS_EMCHUB_MAX_SIZE]; +} BPMP_ABI_PACKED; + +/** @} EMC */ +/** @endcond (bpmp_t234 || bpmp_t239 || bpmp_th500) */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_EMC_DISP_RFL + * @brief Set EMC display RFL handshake mode of operations + * + * * Platforms: T234 onwards + * @cond (bpmp_t234 || bpmp_t239 || bpmp_th500) + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_emc_disp_rfl_request + * * Response Payload: N/A + * + * @addtogroup EMC + * @{ + */ + +enum mrq_emc_disp_rfl_mode { + /** @brief EMC display RFL handshake disabled */ + EMC_DISP_RFL_MODE_DISABLED = 0, + /** @brief EMC display RFL handshake enabled */ + EMC_DISP_RFL_MODE_ENABLED = 1, +}; + +/** + * @ingroup EMC + * @brief Request with #MRQ_EMC_DISP_RFL + * + * Used by the sender of an #MRQ_EMC_DISP_RFL message to + * request the mode of EMC display RFL handshake. + * + * mrq_response::err is + * * 0: RFL mode is set successfully + * * -#BPMP_EINVAL: invalid mode requested + * * -#BPMP_ENOSYS: RFL handshake is not supported + * * -#BPMP_EACCES: Permission denied + * * -#BPMP_ENODEV: if disp rfl mrq is not supported by BPMP-FW + */ +struct mrq_emc_disp_rfl_request { + /** @brief EMC display RFL mode (@ref mrq_emc_disp_rfl_mode) */ + uint32_t mode; +} BPMP_ABI_PACKED; + +/** @} EMC */ +/** @endcond (bpmp_t234 || bpmp_t239 || bpmp_th500) */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_BWMGR + * @brief bwmgr requests + * + * * Platforms: T234 onwards + * @cond (bpmp_t234 || bpmp_t239 || bpmp_th500) + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_bwmgr_request + * * Response Payload: @ref mrq_bwmgr_response + * + * @addtogroup BWMGR + * + * @{ + */ + +enum mrq_bwmgr_cmd { + /** + * @brief Check whether the BPMP driver supports the specified + * request type + * + * mrq_response::err is 0 if the specified request is + * supported and -#BPMP_ENODEV otherwise. + */ + CMD_BWMGR_QUERY_ABI = 0, + + /** + * @brief Determine dram rate to satisfy iso/niso bw requests + * + * mrq_response::err is + * * 0: calc_rate succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_ENOTSUP: Requested bw is not available. + */ + CMD_BWMGR_CALC_RATE = 1 +}; + +/* + * request data for request type CMD_BWMGR_QUERY_ABI + * + * type: Request type for which to check existence. + */ +struct cmd_bwmgr_query_abi_request { + uint32_t type; +} BPMP_ABI_PACKED; + +/** + * @brief Used by @ref cmd_bwmgr_calc_rate_request + */ +struct iso_req { + /* @brief bwmgr client ID @ref bpmp_bwmgr_ids */ + uint32_t id; + /* @brief bw in kBps requested by client */ + uint32_t iso_bw; +} BPMP_ABI_PACKED; + +#define MAX_ISO_CLIENTS 13U +/* + * request data for request type CMD_BWMGR_CALC_RATE + */ +struct cmd_bwmgr_calc_rate_request { + /* @brief total bw in kBps requested by all niso clients */ + uint32_t sum_niso_bw; + /* @brief The number of iso clients */ + uint32_t num_iso_clients; + /* @brief iso_req <id, iso_bw> information */ + struct iso_req isobw_reqs[MAX_ISO_CLIENTS]; +} BPMP_ABI_PACKED; + +/* + * response data for request type CMD_BWMGR_CALC_RATE + * + * iso_rate_min: min dram data clk rate in kHz to satisfy all iso bw reqs + * total_rate_min: min dram data clk rate in kHz to satisfy all bw reqs + */ +struct cmd_bwmgr_calc_rate_response { + uint32_t iso_rate_min; + uint32_t total_rate_min; +} BPMP_ABI_PACKED; + +/* + * @brief Request with #MRQ_BWMGR + * + * + * |sub-command |payload | + * |----------------------------|------------------------------| + * |CMD_BWMGR_QUERY_ABI | cmd_bwmgr_query_abi_request | + * |CMD_BWMGR_CALC_RATE | cmd_bwmgr_calc_rate_request | + * + */ +struct mrq_bwmgr_request { + uint32_t cmd; + union { + struct cmd_bwmgr_query_abi_request query_abi; + struct cmd_bwmgr_calc_rate_request bwmgr_rate_req; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/* + * @brief Response to MRQ_BWMGR + * + * |sub-command |payload | + * |----------------------------|------------------------------| + * |CMD_BWMGR_CALC_RATE | cmd_bwmgr_calc_rate_response | + */ +struct mrq_bwmgr_response { + union { + struct cmd_bwmgr_calc_rate_response bwmgr_rate_resp; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** @} BWMGR */ +/** @endcond (bpmp_t234 || bpmp_t239 || bpmp_th500) */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_BWMGR_INT + * @brief bpmp-integrated bwmgr requests + * + * * Platforms: T234 onwards + * @cond (bpmp_t234 || bpmp_t239 || bpmp_th500) + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_bwmgr_int_request + * * Response Payload: @ref mrq_bwmgr_int_response + * + * @addtogroup BWMGR_INT + * @{ + */ + +enum mrq_bwmgr_int_cmd { + /** + * @brief Check whether the BPMP-FW supports the specified + * request type + * + * mrq_response::err is 0 if the specified request is + * supported and -#BPMP_ENODEV otherwise. + */ + CMD_BWMGR_INT_QUERY_ABI = 1, + + /** + * @brief Determine and set dram rate to satisfy iso/niso bw request + * + * mrq_response::err is + * * 0: request succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + * set_frequency in @ref cmd_bwmgr_int_calc_and_set_response + * will not be set. + * * -#BPMP_ENOTSUP: Requested bw is not available. + * set_frequency in @ref cmd_bwmgr_int_calc_and_set_response + * will be current dram-clk rate. + */ + CMD_BWMGR_INT_CALC_AND_SET = 2, + + /** + * @brief Set a max DRAM frequency for the bandwidth-manager + * + * mrq_response::err is + * * 0: request succeeded. + * * -#BPMP_ENOTSUP: Requested cap frequency is not possible. + */ + CMD_BWMGR_INT_CAP_SET = 3 +}; + +/* + * request structure for request type CMD_BWMGR_QUERY_ABI + * + * type: Request type for which to check existence. + */ +struct cmd_bwmgr_int_query_abi_request { + /* @brief request type determined by @ref mrq_bwmgr_int_cmd */ + uint32_t type; +} BPMP_ABI_PACKED; + +/** + * @defgroup bwmgr_int_unit_type BWMGR_INT floor unit-types + * @addtogroup bwmgr_int_unit_type + * @{ + */ +/** @brief kilobytes per second unit-type */ +#define BWMGR_INT_UNIT_KBPS 0U +/** @brief kilohertz unit-type */ +#define BWMGR_INT_UNIT_KHZ 1U + +/** @} bwmgr_int_unit_type */ + +/* + * request data for request type CMD_BWMGR_INT_CALC_AND_SET + */ +struct cmd_bwmgr_int_calc_and_set_request { + /* @brief bwmgr client ID @ref bpmp_bwmgr_ids */ + uint32_t client_id; + /* @brief average niso bw usage in kBps requested by client. */ + uint32_t niso_bw; + /* + * @brief average iso bw usage in kBps requested by client. + * Value is ignored if client is niso. Determined by client_id. + */ + uint32_t iso_bw; + /* + * @brief memory clock floor requested by client. + * Unit determined by floor_unit. + */ + uint32_t mc_floor; + /* + * @brief toggle to determine the unit-type of floor value. + * See @ref bwmgr_int_unit_type definitions for unit-type mappings. + */ + uint8_t floor_unit; +} BPMP_ABI_PACKED; + +struct cmd_bwmgr_int_cap_set_request { + /* @brief requested cap frequency in Hz. */ + uint64_t rate; +} BPMP_ABI_PACKED; + +/* + * response data for request type CMD_BWMGR_CALC_AND_SET + */ +struct cmd_bwmgr_int_calc_and_set_response { + /* @brief current set memory clock frequency in Hz */ + uint64_t rate; +} BPMP_ABI_PACKED; + +/* + * @brief Request with #MRQ_BWMGR_INT + * + * + * |sub-command |payload | + * |----------------------------|-----------------------------------| + * |CMD_BWMGR_INT_QUERY_ABI | cmd_bwmgr_int_query_abi_request | + * |CMD_BWMGR_INT_CALC_AND_SET | cmd_bwmgr_int_calc_and_set_request| + * |CMD_BWMGR_INT_CAP_SET | cmd_bwmgr_int_cap_set_request | + * + */ +struct mrq_bwmgr_int_request { + uint32_t cmd; + union { + struct cmd_bwmgr_int_query_abi_request query_abi; + struct cmd_bwmgr_int_calc_and_set_request bwmgr_calc_set_req; + struct cmd_bwmgr_int_cap_set_request bwmgr_cap_set_req; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/* + * @brief Response to MRQ_BWMGR_INT + * + * |sub-command |payload | + * |----------------------------|---------------------------------------| + * |CMD_BWMGR_INT_CALC_AND_SET | cmd_bwmgr_int_calc_and_set_response | + */ +struct mrq_bwmgr_int_response { + union { + struct cmd_bwmgr_int_calc_and_set_response bwmgr_calc_set_resp; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** @} BWMGR_INT */ +/** @endcond (bpmp_t234 || bpmp_t239 || bpmp_th500) */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_ISO_CLIENT + * @brief ISO client requests + * + * * Platforms: T234 onwards + * @cond (bpmp_t234 || bpmp_t239 || bpmp_th500) + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_iso_client_request + * * Response Payload: @ref mrq_iso_client_response + * + * @addtogroup ISO_CLIENT + * @{ + */ + +enum mrq_iso_client_cmd { + /** + * @brief Check whether the BPMP driver supports the specified + * request type + * + * mrq_response::err is 0 if the specified request is + * supported and -#BPMP_ENODEV otherwise. + */ + CMD_ISO_CLIENT_QUERY_ABI = 0, + + /* + * @brief check for legal LA for the iso client. Without programming + * LA MC registers, calculate and ensure that legal LA is possible for + * iso bw requested by the ISO client. + * + * mrq_response::err is + * * 0: check la succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_EFAULT: Legal LA is not possible for client requested iso_bw + */ + CMD_ISO_CLIENT_CALCULATE_LA = 1, + + /* + * @brief set LA for the iso client. Calculate and program the LA/PTSA + * MC registers corresponding to the client making bw request + * + * mrq_response::err is + * * 0: set la succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_EFAULT: Failed to calculate or program MC registers. + */ + CMD_ISO_CLIENT_SET_LA = 2, + + /* + * @brief Get max possible bw for iso client + * + * mrq_response::err is + * * 0: get_max_bw succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + */ + CMD_ISO_CLIENT_GET_MAX_BW = 3 +}; + +/* + * request data for request type CMD_ISO_CLIENT_QUERY_ABI + * + * type: Request type for which to check existence. + */ +struct cmd_iso_client_query_abi_request { + uint32_t type; +} BPMP_ABI_PACKED; + +/* + * request data for request type CMD_ISO_CLIENT_CALCULATE_LA + * + * id: client ID in @ref bpmp_bwmgr_ids + * bw: bw requested in kBps by client ID. + * init_bw_floor: initial dram_bw_floor in kBps passed by client ID. + * ISO client will perform mempool allocation and DVFS buffering based + * on this dram_bw_floor. + */ +struct cmd_iso_client_calculate_la_request { + uint32_t id; + uint32_t bw; + uint32_t init_bw_floor; +} BPMP_ABI_PACKED; + +/* + * request data for request type CMD_ISO_CLIENT_SET_LA + * + * id: client ID in @ref bpmp_bwmgr_ids + * bw: bw requested in kBps by client ID. + * final_bw_floor: final dram_bw_floor in kBps. + * Sometimes the initial dram_bw_floor passed by ISO client may need to be + * updated by considering higher dram freq's. This is the final dram_bw_floor + * used to calculate and program MC registers. + */ +struct cmd_iso_client_set_la_request { + uint32_t id; + uint32_t bw; + uint32_t final_bw_floor; +} BPMP_ABI_PACKED; + +/* + * request data for request type CMD_ISO_CLIENT_GET_MAX_BW + * + * id: client ID in @ref bpmp_bwmgr_ids + */ +struct cmd_iso_client_get_max_bw_request { + uint32_t id; +} BPMP_ABI_PACKED; + +/* + * response data for request type CMD_ISO_CLIENT_CALCULATE_LA + * + * la_rate_floor: minimum dram_rate_floor in kHz at which a legal la is possible + * iso_client_only_rate: Minimum dram freq in kHz required to satisfy this clients + * iso bw request, assuming all other iso clients are inactive + */ +struct cmd_iso_client_calculate_la_response { + uint32_t la_rate_floor; + uint32_t iso_client_only_rate; +} BPMP_ABI_PACKED; + +/** + * @brief Used by @ref cmd_iso_client_get_max_bw_response + */ +struct iso_max_bw { + /* @brief dram frequency in kHz */ + uint32_t freq; + /* @brief max possible iso-bw in kBps */ + uint32_t iso_bw; +} BPMP_ABI_PACKED; + +#define ISO_MAX_BW_MAX_SIZE 14U +/* + * response data for request type CMD_ISO_CLIENT_GET_MAX_BW + */ +struct cmd_iso_client_get_max_bw_response { + /* @brief The number valid entries in iso_max_bw pairs */ + uint32_t num_pairs; + /* @brief max ISOBW <dram freq, max bw> information */ + struct iso_max_bw pairs[ISO_MAX_BW_MAX_SIZE]; +} BPMP_ABI_PACKED; + +/** + * @brief Request with #MRQ_ISO_CLIENT + * + * Used by the sender of an #MRQ_ISO_CLIENT message. + * + * |sub-command |payload | + * |------------------------------------ |----------------------------------------| + * |CMD_ISO_CLIENT_QUERY_ABI |cmd_iso_client_query_abi_request | + * |CMD_ISO_CLIENT_CALCULATE_LA |cmd_iso_client_calculate_la_request | + * |CMD_ISO_CLIENT_SET_LA |cmd_iso_client_set_la_request | + * |CMD_ISO_CLIENT_GET_MAX_BW |cmd_iso_client_get_max_bw_request | + * + */ + +struct mrq_iso_client_request { + /* Type of request. Values listed in enum mrq_iso_client_cmd */ + uint32_t cmd; + union { + struct cmd_iso_client_query_abi_request query_abi; + struct cmd_iso_client_calculate_la_request calculate_la_req; + struct cmd_iso_client_set_la_request set_la_req; + struct cmd_iso_client_get_max_bw_request max_isobw_req; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** + * @brief Response to MRQ_ISO_CLIENT + * + * Each sub-command supported by @ref mrq_iso_client_request may return + * sub-command-specific data. Some do and some do not as indicated in + * the following table + * + * |sub-command |payload | + * |---------------------------- |------------------------------------| + * |CMD_ISO_CLIENT_CALCULATE_LA |cmd_iso_client_calculate_la_response| + * |CMD_ISO_CLIENT_SET_LA |N/A | + * |CMD_ISO_CLIENT_GET_MAX_BW |cmd_iso_client_get_max_bw_response | + * + */ + +struct mrq_iso_client_response { + union { + struct cmd_iso_client_calculate_la_response calculate_la_resp; + struct cmd_iso_client_get_max_bw_response max_isobw_resp; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** @} ISO_CLIENT */ +/** @endcond (bpmp_t234 || bpmp_t239 || bpmp_th500) */ /** * @ingroup MRQ_Codes @@ -2061,7 +2644,7 @@ struct mrq_emc_dvfs_latency_response { * @brief CPU freq. limits in ndiv * * * Platforms: T194 onwards - * @cond bpmp_t194 + * @cond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_cpu_ndiv_limits_request @@ -2094,15 +2677,15 @@ struct mrq_cpu_ndiv_limits_response { uint16_t ndiv_min; } BPMP_ABI_PACKED; -/** @} */ -/** @endcond */ +/** @} CPU */ +/** @endcond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) */ /** * @ingroup MRQ_Codes * @def MRQ_CPU_AUTO_CC3 * @brief Query CPU cluster auto-CC3 configuration * - * * Platforms: T194 onwards + * * Platforms: T194 * @cond bpmp_t194 * * Initiators: CCPLEX * * Targets: BPMP @@ -2140,40 +2723,8 @@ struct mrq_cpu_auto_cc3_response { uint32_t auto_cc3_config; } BPMP_ABI_PACKED; -/** @} */ -/** @endcond */ - -/** - * @ingroup MRQ_Codes - * @def MRQ_TRACE_ITER - * @brief Manage the trace iterator - * - * @deprecated - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: N/A - * * Response Payload: @ref mrq_trace_iter_request - * @addtogroup Trace - * @{ - */ -enum { - /** @brief (re)start the tracing now. Ignore older events */ - TRACE_ITER_INIT = 0, - /** @brief Clobber all events in the trace buffer */ - TRACE_ITER_CLEAN = 1 -}; - -/** - * @brief Request with #MRQ_TRACE_ITER - */ -struct mrq_trace_iter_request { - /** @brief TRACE_ITER_INIT or TRACE_ITER_CLEAN */ - uint32_t cmd; -} BPMP_ABI_PACKED; - -/** @} */ +/** @} CC3 */ +/** @endcond bpmp_t194 */ /** * @ingroup MRQ_Codes @@ -2351,7 +2902,8 @@ union mrq_ringbuf_console_bpmp_to_host_response { struct cmd_ringbuf_console_write_resp write; struct cmd_ringbuf_console_get_fifo_resp get_fifo; } BPMP_ABI_PACKED; -/** @} */ + +/** @} RingbufConsole */ /** * @ingroup MRQ_Codes @@ -2359,7 +2911,7 @@ union mrq_ringbuf_console_bpmp_to_host_response { * @brief Set a strap value controlled by BPMP * * * Platforms: T194 onwards - * @cond bpmp_t194 + * @cond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_strap_request @@ -2390,17 +2942,14 @@ enum mrq_strap_cmd { struct mrq_strap_request { /** @brief @ref mrq_strap_cmd */ uint32_t cmd; - /** @brief Strap ID from @ref Strap_Ids */ + /** @brief Strap ID from @ref Strap_Identifiers */ uint32_t id; /** @brief Desired value for strap (if cmd is #STRAP_SET) */ uint32_t value; } BPMP_ABI_PACKED; -/** - * @defgroup Strap_Ids Strap Identifiers - * @} - */ -/** @endcond */ +/** @} Strap */ +/** @endcond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) */ /** * @ingroup MRQ_Codes @@ -2408,7 +2957,7 @@ struct mrq_strap_request { * @brief Perform a UPHY operation * * * Platforms: T194 onwards - * @cond bpmp_t194 + * @cond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_uphy_request @@ -2423,6 +2972,9 @@ enum { CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT = 3, CMD_UPHY_PCIE_CONTROLLER_STATE = 4, CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF = 5, + CMD_UPHY_DISPLAY_PORT_INIT = 6, + CMD_UPHY_DISPLAY_PORT_OFF = 7, + CMD_UPHY_XUSB_DYN_LANES_RESTORE = 8, CMD_UPHY_MAX, }; @@ -2445,28 +2997,41 @@ struct cmd_uphy_margin_status_response { } BPMP_ABI_PACKED; struct cmd_uphy_ep_controller_pll_init_request { - /** @brief EP controller number, valid: 0, 4, 5 */ + /** @brief EP controller number, T194 valid: 0, 4, 5; T234 valid: 5, 6, 7, 10; T239 valid: 0 */ uint8_t ep_controller; } BPMP_ABI_PACKED; struct cmd_uphy_pcie_controller_state_request { - /** @brief PCIE controller number, valid: 0, 1, 2, 3, 4 */ + /** @brief PCIE controller number, T194 valid: 0-4; T234 valid: 0-10; T239 valid: 0-3 */ uint8_t pcie_controller; uint8_t enable; } BPMP_ABI_PACKED; struct cmd_uphy_ep_controller_pll_off_request { - /** @brief EP controller number, valid: 0, 4, 5 */ + /** @brief EP controller number, T194 valid: 0, 4, 5; T234 valid: 5, 6, 7, 10; T239 valid: 0 */ uint8_t ep_controller; } BPMP_ABI_PACKED; +struct cmd_uphy_display_port_init_request { + /** @brief DisplayPort link rate, T239 valid: 1620, 2700, 5400, 8100, 2160, 2430, 3240, 4320, 6750 */ + uint16_t link_rate; + /** @brief 1: lane 0; 2: lane 1; 3: lane 0 and 1 */ + uint16_t lanes_bitmap; +} BPMP_ABI_PACKED; + +struct cmd_uphy_xusb_dyn_lanes_restore_request { + /** @brief 1: lane 0; 2: lane 1; 3: lane 0 and 1 */ + uint16_t lanes_bitmap; +} BPMP_ABI_PACKED; + /** * @ingroup UPHY * @brief Request with #MRQ_UPHY * - * Used by the sender of an #MRQ_UPHY message to control UPHY Lane RX margining. - * The uphy_request is split into several sub-commands. Some sub-commands - * require no additional data. Others have a sub-command specific payload + * Used by the sender of an #MRQ_UPHY message to control UPHY. + * The uphy_request is split into several sub-commands. CMD_UPHY_PCIE_LANE_MARGIN_STATUS + * requires no additional data. Others have a sub-command specific payload. Below table + * shows sub-commands with their corresponding payload data. * * |sub-command |payload | * |------------------------------------ |----------------------------------------| @@ -2475,6 +3040,9 @@ struct cmd_uphy_ep_controller_pll_off_request { * |CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT |cmd_uphy_ep_controller_pll_init_request | * |CMD_UPHY_PCIE_CONTROLLER_STATE |cmd_uphy_pcie_controller_state_request | * |CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF |cmd_uphy_ep_controller_pll_off_request | + * |CMD_UPHY_PCIE_DISPLAY_PORT_INIT |cmd_uphy_display_port_init_request | + * |CMD_UPHY_PCIE_DISPLAY_PORT_OFF | | + * |CMD_UPHY_XUSB_DYN_LANES_RESTORE |cmd_uphy_xusb_dyn_lanes_restore_request | * */ @@ -2489,6 +3057,8 @@ struct mrq_uphy_request { struct cmd_uphy_ep_controller_pll_init_request ep_ctrlr_pll_init; struct cmd_uphy_pcie_controller_state_request controller_state; struct cmd_uphy_ep_controller_pll_off_request ep_ctrlr_pll_off; + struct cmd_uphy_display_port_init_request display_port_init; + struct cmd_uphy_xusb_dyn_lanes_restore_request xusb_dyn_lanes_restore; } BPMP_UNION_ANON; } BPMP_ABI_PACKED; @@ -2513,8 +3083,8 @@ struct mrq_uphy_response { } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ -/** @endcond */ +/** @} UPHY */ +/** @endcond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) */ /** * @ingroup MRQ_Codes @@ -2522,14 +3092,16 @@ struct mrq_uphy_response { * @brief Perform a frequency monitor configuration operations * * * Platforms: T194 onwards - * @cond bpmp_t194 + * @cond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_fmon_request * * Response Payload: @ref mrq_fmon_response + * @endcond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) * * @addtogroup FMON * @{ + * @cond (bpmp_t194 || bpmp_t234) */ enum { /** @@ -2538,6 +3110,20 @@ enum { * The monitored clock must be running for clamp to succeed. If * clamped, FMON configuration is preserved when clock rate * and/or state is changed. + * + * mrq_response::err is 0 if the operation was successful, or @n + * -#BPMP_EACCES: FMON access error @n + * -#BPMP_EBADCMD if subcommand is not supported @n + * -#BPMP_EBADSLT: clamp FMON on cluster with auto-CC3 enabled @n + * -#BPMP_EBUSY: fmon is already clamped at different rate @n + * -#BPMP_EFAULT: self-diagnostic error @n + * -#BPMP_EINVAL: invalid FMON configuration @n + * -#BPMP_EOPNOTSUPP: not in production mode @n + * -#BPMP_ENODEV: invalid clk_id @n + * -#BPMP_ENOENT: no calibration data, uninitialized @n + * -#BPMP_ENOTSUP: avfs config not set @n + * -#BPMP_ENOSYS: clamp FMON on cluster clock w/ no NAFLL @n + * -#BPMP_ETIMEDOUT: operation timed out @n */ CMD_FMON_GEAR_CLAMP = 1, /** @@ -2545,6 +3131,13 @@ enum { * * Allow FMON configuration to follow monitored clock rate * and/or state changes. + * + * mrq_response::err is 0 if the operation was successful, or @n + * -#BPMP_EBADCMD if subcommand is not supported @n + * -#BPMP_ENODEV: invalid clk_id @n + * -#BPMP_ENOENT: no calibration data, uninitialized @n + * -#BPMP_ENOTSUP: avfs config not set @n + * -#BPMP_EOPNOTSUPP: not in production mode @n */ CMD_FMON_GEAR_FREE = 2, /** @@ -2553,11 +3146,54 @@ enum { * * Inherently racy, since clamp state can be changed * concurrently. Useful for testing. + * + * mrq_response::err is 0 if the operation was successful, or @n + * -#BPMP_EBADCMD if subcommand is not supported @n + * -#BPMP_ENODEV: invalid clk_id @n + * -#BPMP_ENOENT: no calibration data, uninitialized @n + * -#BPMP_ENOTSUP: avfs config not set @n + * -#BPMP_EOPNOTSUPP: not in production mode @n */ CMD_FMON_GEAR_GET = 3, - CMD_FMON_NUM, + /** + * @brief Return current status of FMON faults detected by FMON + * h/w or s/w since last invocation of this command. + * Clears fault status. + * + * mrq_response::err is 0 if the operation was successful, or @n + * -#BPMP_EBADCMD if subcommand is not supported @n + * -#BPMP_EINVAL: invalid fault type @n + * -#BPMP_ENODEV: invalid clk_id @n + * -#BPMP_ENOENT: no calibration data, uninitialized @n + * -#BPMP_ENOTSUP: avfs config not set @n + * -#BPMP_EOPNOTSUPP: not in production mode @n + */ + CMD_FMON_FAULT_STS_GET = 4, }; +/** + * @cond DEPRECATED + * Kept for backward compatibility + */ +#define CMD_FMON_NUM 4 + +/** @endcond DEPRECATED */ + +/** + * @defgroup fmon_fault_type FMON fault type + * @addtogroup fmon_fault_type + * @{ + */ +/** @brief All detected FMON faults (h/w or s/w) */ +#define FMON_FAULT_TYPE_ALL 0U +/** @brief FMON faults detected by h/w */ +#define FMON_FAULT_TYPE_HW 1U +/** @brief FMON faults detected by s/w */ +#define FMON_FAULT_TYPE_SW 2U + +/** @} fmon_fault_type */ + + struct cmd_fmon_gear_clamp_request { int32_t unused; int64_t rate; @@ -2587,6 +3223,14 @@ struct cmd_fmon_gear_get_response { int64_t rate; } BPMP_ABI_PACKED; +struct cmd_fmon_fault_sts_get_request { + uint32_t fault_type; /**< @ref fmon_fault_type */ +} BPMP_ABI_PACKED; + +struct cmd_fmon_fault_sts_get_response { + uint32_t fault_sts; +} BPMP_ABI_PACKED; + /** * @ingroup FMON * @brief Request with #MRQ_FMON @@ -2601,9 +3245,9 @@ struct cmd_fmon_gear_get_response { * |CMD_FMON_GEAR_CLAMP |fmon_gear_clamp | * |CMD_FMON_GEAR_FREE |- | * |CMD_FMON_GEAR_GET |- | + * |CMD_FMON_FAULT_STS_GET |fmon_fault_sts_get | * */ - struct mrq_fmon_request { /** @brief Sub-command and clock id concatenated to 32-bit word. * - bits[31..24] is the sub-cmd. @@ -2618,6 +3262,7 @@ struct mrq_fmon_request { struct cmd_fmon_gear_free_request fmon_gear_free; /** @private */ struct cmd_fmon_gear_get_request fmon_gear_get; + struct cmd_fmon_fault_sts_get_request fmon_fault_sts_get; } BPMP_UNION_ANON; } BPMP_ABI_PACKED; @@ -2633,6 +3278,7 @@ struct mrq_fmon_request { * |CMD_FMON_GEAR_CLAMP |- | * |CMD_FMON_GEAR_FREE |- | * |CMD_FMON_GEAR_GET |fmon_gear_get | + * |CMD_FMON_FAULT_STS_GET |fmon_fault_sts_get | * */ @@ -2643,11 +3289,12 @@ struct mrq_fmon_response { /** @private */ struct cmd_fmon_gear_free_response fmon_gear_free; struct cmd_fmon_gear_get_response fmon_gear_get; + struct cmd_fmon_fault_sts_get_response fmon_fault_sts_get; } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ -/** @endcond */ +/** @endcond (bpmp_t194 || bpmp_t234) */ +/** @} FMON */ /** * @ingroup MRQ_Codes @@ -2655,7 +3302,7 @@ struct mrq_fmon_response { * @brief Provide status information on faults reported by Error * Collator (EC) to HSM. * - * * Platforms: T194 onwards + * * Platforms: T194 * @cond bpmp_t194 * * Initiators: CCPLEX * * Targets: BPMP @@ -2664,8 +3311,10 @@ struct mrq_fmon_response { * * @note This MRQ ABI is under construction, and subject to change * + * @endcond bpmp_t194 * @addtogroup EC * @{ + * @cond bpmp_t194 */ enum { /** @@ -2676,7 +3325,7 @@ enum { * -#BPMP_ENODEV if target EC is not owned by BPMP @n * -#BPMP_EACCES if target EC power domain is turned off @n * -#BPMP_EBADCMD if subcommand is not supported - * @endcond + * @endcond DEPRECATED */ CMD_EC_STATUS_GET = 1, /* deprecated */ @@ -2787,7 +3436,8 @@ enum ec_registers_group { #define EC_STATUS_FLAG_LAST_ERROR 0x0002U /** @brief EC latent error flag */ #define EC_STATUS_FLAG_LATENT_ERROR 0x0004U -/** @} */ + +/** @} bpmp_ec_status_flags */ /** * @defgroup bpmp_ec_desc_flags EC Descriptor Flags @@ -2798,7 +3448,8 @@ enum ec_registers_group { #define EC_DESC_FLAG_RESOLVED 0x0001U /** @brief EC descriptor failed to retrieve id flag */ #define EC_DESC_FLAG_NO_ID 0x0002U -/** @} */ + +/** @} bpmp_ec_desc_flags */ /** * |error type | fmon_clk_id values | @@ -2810,14 +3461,18 @@ struct ec_err_fmon_desc { uint16_t desc_flags; /** @brief FMON monitored clock id */ uint16_t fmon_clk_id; - /** @brief Bitmask of @ref bpmp_fmon_faults_flags */ + /** + * @brief Bitmask of fault flags + * + * @ref bpmp_fmon_faults_flags + */ uint32_t fmon_faults; /** @brief FMON faults access error */ int32_t fmon_access_error; } BPMP_ABI_PACKED; /** - * |error type | vmon_adc_id values | + * | error type | vmon_adc_id values | * |---------------------------------|---------------------------| * |@ref EC_ERR_TYPE_VOLTAGE_MONITOR |@ref bpmp_adc_ids | */ @@ -2826,16 +3481,16 @@ struct ec_err_vmon_desc { uint16_t desc_flags; /** @brief VMON rail adc id */ uint16_t vmon_adc_id; - /** @brief Bitmask of @ref bpmp_vmon_faults_flags */ + /** @brief Bitmask of bpmp_vmon_faults_flags */ uint32_t vmon_faults; /** @brief VMON faults access error */ int32_t vmon_access_error; } BPMP_ABI_PACKED; /** - * |error type | reg_id values | - * |---------------------------------|---------------------------| - * |@ref EC_ERR_TYPE_REGISTER_PARITY |@ref bpmp_ec_registers_ids | + * |error type | reg_id values | + * |---------------------------------|-----------------------| + * |@ref EC_ERR_TYPE_REGISTER_PARITY | bpmp_ec_registers_ids | */ struct ec_err_reg_parity_desc { /** @brief Bitmask of @ref bpmp_ec_desc_flags */ @@ -2847,10 +3502,10 @@ struct ec_err_reg_parity_desc { } BPMP_ABI_PACKED; /** - * |error type | err_source_id values | - * |--------------------------------- |--------------------------| - * |@ref EC_ERR_TYPE_SW_CORRECTABLE | @ref bpmp_ec_ce_swd_ids | - * |@ref EC_ERR_TYPE_SW_UNCORRECTABLE | @ref bpmp_ec_ue_swd_ids | + * |error type | err_source_id values | + * |--------------------------------- |----------------------| + * |@ref EC_ERR_TYPE_SW_CORRECTABLE | bpmp_ec_ce_swd_ids | + * |@ref EC_ERR_TYPE_SW_UNCORRECTABLE | bpmp_ec_ue_swd_ids | */ struct ec_err_sw_error_desc { /** @brief Bitmask of @ref bpmp_ec_desc_flags */ @@ -2862,15 +3517,15 @@ struct ec_err_sw_error_desc { } BPMP_ABI_PACKED; /** - * |error type | err_source_id values | - * |----------------------------------------|---------------------------| - * |@ref EC_ERR_TYPE_PARITY_INTERNAL |@ref bpmp_ec_ipath_ids | - * |@ref EC_ERR_TYPE_ECC_SEC_INTERNAL |@ref bpmp_ec_ipath_ids | - * |@ref EC_ERR_TYPE_ECC_DED_INTERNAL |@ref bpmp_ec_ipath_ids | - * |@ref EC_ERR_TYPE_COMPARATOR |@ref bpmp_ec_comparator_ids| - * |@ref EC_ERR_TYPE_PARITY_SRAM |@ref bpmp_clock_ids | - * |@ref EC_ERR_TYPE_OTHER_HW_CORRECTABLE |@ref bpmp_ec_misc_hwd_ids | - * |@ref EC_ERR_TYPE_OTHER_HW_UNCORRECTABLE |@ref bpmp_ec_misc_hwd_ids | + * |error type | err_source_id values | + * |----------------------------------------|------------------------| + * |@ref EC_ERR_TYPE_PARITY_INTERNAL | bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_ECC_SEC_INTERNAL | bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_ECC_DED_INTERNAL | bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_COMPARATOR | bpmp_ec_comparator_ids| + * |@ref EC_ERR_TYPE_OTHER_HW_CORRECTABLE | bpmp_ec_misc_hwd_ids | + * |@ref EC_ERR_TYPE_OTHER_HW_UNCORRECTABLE | bpmp_ec_misc_hwd_ids | + * |@ref EC_ERR_TYPE_PARITY_SRAM | bpmp_clock_ids | */ struct ec_err_simple_desc { /** @brief Bitmask of @ref bpmp_ec_desc_flags */ @@ -2917,7 +3572,7 @@ struct cmd_ec_status_get_response { /** @brief EC error descriptors */ union ec_err_desc error_descs[EC_ERR_STATUS_DESC_MAX_NUM]; } BPMP_ABI_PACKED; -/** @endcond */ +/** @endcond DEPRECATED */ struct cmd_ec_status_ex_get_response { /** @brief Target EC id (the same id received with request). */ @@ -2955,7 +3610,7 @@ struct cmd_ec_status_ex_get_response { * |sub-command |payload | * |----------------------------|-----------------------| * |@ref CMD_EC_STATUS_GET |ec_status_get | - * @endcond + * @endcond DEPRECATED * * |sub-command |payload | * |----------------------------|-----------------------| @@ -2983,7 +3638,7 @@ struct mrq_ec_request { * |sub-command |payload | * |----------------------------|------------------------| * |@ref CMD_EC_STATUS_GET |ec_status_get | - * @endcond + * @endcond DEPRECATED * * |sub-command |payload | * |----------------------------|------------------------| @@ -2997,13 +3652,264 @@ struct mrq_ec_response { * @cond DEPRECATED */ struct cmd_ec_status_get_response ec_status_get; - /** @endcond */ + /** @endcond DEPRECATED */ struct cmd_ec_status_ex_get_response ec_status_ex_get; } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ -/** @endcond */ +/** @endcond bpmp_t194 */ +/** @} EC */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_TELEMETRY + * @brief Get address of memory buffer refreshed with recently sampled + * telemetry data + * + * * Platforms: TH500 onwards + * @cond bpmp_th500 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_telemetry_response + * @addtogroup Telemetry + * @{ + */ + +/** + * @brief Response to #MRQ_TELEMETRY + * + * mrq_response::err is + * * 0: Telemetry data is available at returned address + * * -#BPMP_EACCES: MRQ master is not allowed to request buffer refresh + * * -#BPMP_ENAVAIL: Telemetry buffer cannot be refreshed via this MRQ channel + * * -#BPMP_ENOTSUP: Telemetry buffer is not supported by BPMP-FW + * * -#BPMP_ENODEV: Telemetry mrq is not supported by BPMP-FW + */ +struct mrq_telemetry_response { + /** @brief Physical address of telemetry data buffer */ + uint64_t data_buf_addr; /**< see @ref bpmp_telemetry_layout */ +} BPMP_ABI_PACKED; + +/** @} Telemetry */ +/** @endcond bpmp_th500 */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_PWR_LIMIT + * @brief Control power limits. + * + * * Platforms: TH500 onwards + * @cond bpmp_th500 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_pwr_limit_request + * * Response Payload: @ref mrq_pwr_limit_response + * + * @addtogroup Pwrlimit + * @{ + */ +enum mrq_pwr_limit_cmd { + /** + * @brief Check whether the BPMP-FW supports the specified + * command + * + * mrq_response::err is 0 if the specified request is + * supported and -#BPMP_ENODEV otherwise. + */ + CMD_PWR_LIMIT_QUERY_ABI = 0, + + /** + * @brief Set power limit + * + * mrq_response:err is + * * 0: Success + * * -#BPMP_ENODEV: Pwr limit mrq is not supported by BPMP-FW + * * -#BPMP_ENAVAIL: Invalid request parameters + * * -#BPMP_EACCES: Request is not accepted + */ + CMD_PWR_LIMIT_SET = 1, + + /** + * @brief Get power limit setting + * + * mrq_response:err is + * * 0: Success + * * -#BPMP_ENODEV: Pwr limit mrq is not supported by BPMP-FW + * * -#BPMP_ENAVAIL: Invalid request parameters + */ + CMD_PWR_LIMIT_GET = 2, + + /** + * @brief Get current power cap + * + * mrq_response:err is + * * 0: Success + * * -#BPMP_ENODEV: Pwr limit mrq is not supported by BPMP-FW + * * -#BPMP_ENAVAIL: Invalid request parameters + */ + CMD_PWR_LIMIT_CURR_CAP = 3, +}; + +/** + * @defgroup bpmp_pwr_limit_type PWR_LIMIT TYPEs + * @{ + */ +/** @brief Limit value specifies traget cap */ +#define PWR_LIMIT_TYPE_TARGET_CAP 0U +/** @brief Limit value specifies maximum possible target cap */ +#define PWR_LIMIT_TYPE_BOUND_MAX 1U +/** @brief Limit value specifies minimum possible target cap */ +#define PWR_LIMIT_TYPE_BOUND_MIN 2U +/** @brief Number of limit types supported by mrq interface */ +#define PWR_LIMIT_TYPE_NUM 3U + +/** @} bpmp_pwr_limit_type */ + +/** + * @brief Request data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_QUERY_ABI + */ +struct cmd_pwr_limit_query_abi_request { + uint32_t cmd_code; /**< @ref mrq_pwr_limit_cmd */ +} BPMP_ABI_PACKED; + +/** + * @brief Request data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_SET + * + * Set specified limit of specified type from specified source. The success of + * the request means that specified value is accepted as input to arbitration + * with other sources settings for the same limit of the same type. Zero limit + * is ignored by the arbitration (i.e., indicates "no limit set"). + */ +struct cmd_pwr_limit_set_request { + uint32_t limit_id; /**< @ref bpmp_pwr_limit_id */ + uint32_t limit_src; /**< @ref bpmp_pwr_limit_src */ + uint32_t limit_type; /**< @ref bpmp_pwr_limit_type */ + uint32_t limit_setting; +} BPMP_ABI_PACKED; + +/** + * @brief Request data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_GET + * + * Get previously set from specified source specified limit value of specified + * type. + */ +struct cmd_pwr_limit_get_request { + uint32_t limit_id; /**< @ref bpmp_pwr_limit_id */ + uint32_t limit_src; /**< @ref bpmp_pwr_limit_src */ + uint32_t limit_type; /**< @ref bpmp_pwr_limit_type */ +} BPMP_ABI_PACKED; + +/** + * @brief Response data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_GET + */ +struct cmd_pwr_limit_get_response { + uint32_t limit_setting; +} BPMP_ABI_PACKED; + +/** + * @brief Request data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_CURR_CAP + * + * For specified limit get current power cap aggregated from all sources. + */ +struct cmd_pwr_limit_curr_cap_request { + uint32_t limit_id; /**< @ref bpmp_pwr_limit_id */ +} BPMP_ABI_PACKED; + +/** + * @brief Response data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_CURR_CAP + */ +struct cmd_pwr_limit_curr_cap_response { + uint32_t curr_cap; +} BPMP_ABI_PACKED; + +/** + * @brief Request with #MRQ_PWR_LIMIT + * + * |sub-command |payload | + * |----------------------------|---------------------------------| + * |CMD_PWR_LIMIT_QUERY_ABI | cmd_pwr_limit_query_abi_request | + * |CMD_PWR_LIMIT_SET | cmd_pwr_limit_set_request | + * |CMD_PWR_LIMIT_GET | cmd_pwr_limit_get_request | + * |CMD_PWR_LIMIT_CURR_CAP | cmd_pwr_limit_curr_cap_request | + */ +struct mrq_pwr_limit_request { + uint32_t cmd; + union { + struct cmd_pwr_limit_query_abi_request pwr_limit_query_abi_req; + struct cmd_pwr_limit_set_request pwr_limit_set_req; + struct cmd_pwr_limit_get_request pwr_limit_get_req; + struct cmd_pwr_limit_curr_cap_request pwr_limit_curr_cap_req; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** + * @brief Response to MRQ_PWR_LIMIT + * + * |sub-command |payload | + * |----------------------------|---------------------------------| + * |CMD_PWR_LIMIT_QUERY_ABI | - | + * |CMD_PWR_LIMIT_SET | - | + * |CMD_PWR_LIMIT_GET | cmd_pwr_limit_get_response | + * |CMD_PWR_LIMIT_CURR_CAP | cmd_pwr_limit_curr_cap_response | + */ +struct mrq_pwr_limit_response { + union { + struct cmd_pwr_limit_get_response pwr_limit_get_rsp; + struct cmd_pwr_limit_curr_cap_response pwr_limit_curr_cap_rsp; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** @} PwrLimit */ +/** @endcond bpmp_th500 */ + + +/** + * @ingroup MRQ_Codes + * @def MRQ_GEARS + * @brief Get thresholds for NDIV offset switching + * + * * Platforms: TH500 onwards + * @cond bpmp_th500 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_gears_response + * @addtogroup Gears + * @{ + */ + +/** + * @brief Response to #MRQ_GEARS + * + * Used by the sender of an #MRQ_GEARS message to request thresholds + * for NDIV offset switching. + * + * The mrq_gears_response::ncpu array defines four thresholds in units + * of number of online CPUS to be used for choosing between five different + * NDIV offset settings for CCPLEX cluster NAFLLs + * + * 1. If number of online CPUs < ncpu[0] use offset0 + * 2. If number of online CPUs < ncpu[1] use offset1 + * 3. If number of online CPUs < ncpu[2] use offset2 + * 4. If number of online CPUs < ncpu[3] use offset3 + * 5. If number of online CPUs >= ncpu[3] disable offsetting + * + * For TH500 mrq_gears_response::ncpu array has four valid entries. + * + * mrq_response::err is + * * 0: gears defined and response data valid + * * -#BPMP_ENODEV: MRQ is not supported by BPMP-FW + * * -#BPMP_EACCES: Operation not permitted for the MRQ master + * * -#BPMP_ENAVAIL: NDIV offsetting is disabled + */ +struct mrq_gears_response { + /** @brief number of online CPUs for each gear */ + uint32_t ncpu[16]; +} BPMP_ABI_PACKED; + +/** @} Gears */ +/** @endcond bpmp_th500 */ /** * @addtogroup Error_Codes @@ -3047,12 +3953,18 @@ struct mrq_ec_response { #define BPMP_ENOSYS 38 /** @brief Invalid slot */ #define BPMP_EBADSLT 57 +/** @brief Invalid message */ +#define BPMP_EBADMSG 77 +/** @brief Operation not supported */ +#define BPMP_EOPNOTSUPP 95 +/** @brief Targeted resource not available */ +#define BPMP_ENAVAIL 119 /** @brief Not supported */ #define BPMP_ENOTSUP 134 /** @brief No such device or address */ #define BPMP_ENXIO 140 -/** @} */ +/** @} Error_Codes */ #if defined(BPMP_ABI_CHECKS) #include "bpmp_abi_checks.h" diff --git a/include/soc/tegra/bpmp.h b/include/soc/tegra/bpmp.h index f2604e99af09..5842e38bb288 100644 --- a/include/soc/tegra/bpmp.h +++ b/include/soc/tegra/bpmp.h @@ -6,6 +6,7 @@ #ifndef __SOC_TEGRA_BPMP_H #define __SOC_TEGRA_BPMP_H +#include <linux/iosys-map.h> #include <linux/mailbox_client.h> #include <linux/pm_domain.h> #include <linux/reset-controller.h> @@ -36,10 +37,22 @@ struct tegra_bpmp_mb_data { u8 data[MSG_DATA_MIN_SZ]; } __packed; +#define tegra_bpmp_mb_read(dst, mb, size) \ + iosys_map_memcpy_from(dst, mb, offsetof(struct tegra_bpmp_mb_data, data), size) + +#define tegra_bpmp_mb_write(mb, src, size) \ + iosys_map_memcpy_to(mb, offsetof(struct tegra_bpmp_mb_data, data), src, size) + +#define tegra_bpmp_mb_read_field(mb, field) \ + iosys_map_rd_field(mb, 0, struct tegra_bpmp_mb_data, field) + +#define tegra_bpmp_mb_write_field(mb, field, value) \ + iosys_map_wr_field(mb, 0, struct tegra_bpmp_mb_data, field, value) + struct tegra_bpmp_channel { struct tegra_bpmp *bpmp; - struct tegra_bpmp_mb_data *ib; - struct tegra_bpmp_mb_data *ob; + struct iosys_map ib; + struct iosys_map ob; struct completion completion; struct tegra_ivc *ivc; unsigned int index; diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index 977c334136e9..a63de5da8124 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -34,6 +34,20 @@ enum tegra_revision { TEGRA_REVISION_MAX, }; +enum tegra_platform { + TEGRA_PLATFORM_SILICON = 0, + TEGRA_PLATFORM_QT, + TEGRA_PLATFORM_SYSTEM_FPGA, + TEGRA_PLATFORM_UNIT_FPGA, + TEGRA_PLATFORM_ASIM_QT, + TEGRA_PLATFORM_ASIM_LINSIM, + TEGRA_PLATFORM_DSIM_ASIM_LINSIM, + TEGRA_PLATFORM_VERIFICATION_SIMULATION, + TEGRA_PLATFORM_VDK, + TEGRA_PLATFORM_VSP, + TEGRA_PLATFORM_MAX, +}; + struct tegra_sku_info { int sku_id; int cpu_process_id; @@ -47,6 +61,7 @@ struct tegra_sku_info { int gpu_speedo_id; int gpu_speedo_value; enum tegra_revision revision; + enum tegra_platform platform; }; #ifdef CONFIG_ARCH_TEGRA diff --git a/include/soc/tegra/ivc.h b/include/soc/tegra/ivc.h index 4aeb77cc22c5..be45d5f5adea 100644 --- a/include/soc/tegra/ivc.h +++ b/include/soc/tegra/ivc.h @@ -4,9 +4,11 @@ */ #ifndef __TEGRA_IVC_H +#define __TEGRA_IVC_H #include <linux/device.h> #include <linux/dma-mapping.h> +#include <linux/iosys-map.h> #include <linux/types.h> struct tegra_ivc_header; @@ -15,7 +17,7 @@ struct tegra_ivc { struct device *peer; struct { - struct tegra_ivc_header *channel; + struct iosys_map map; unsigned int position; dma_addr_t phys; } rx, tx; @@ -36,7 +38,7 @@ struct tegra_ivc { * * Returns a pointer to the frame, or an error encoded pointer. */ -void *tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc); +int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, struct iosys_map *map); /** * tegra_ivc_read_advance - Advance the read queue @@ -56,7 +58,7 @@ int tegra_ivc_read_advance(struct tegra_ivc *ivc); * * Returns a pointer to the frame, or an error encoded pointer. */ -void *tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc); +int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, struct iosys_map *map); /** * tegra_ivc_write_advance - Advance the write queue @@ -91,8 +93,8 @@ void tegra_ivc_reset(struct tegra_ivc *ivc); size_t tegra_ivc_align(size_t size); unsigned tegra_ivc_total_queue_size(unsigned queue_size); -int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, void *rx, - dma_addr_t rx_phys, void *tx, dma_addr_t tx_phys, +int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, const struct iosys_map *rx, + dma_addr_t rx_phys, const struct iosys_map *tx, dma_addr_t tx_phys, unsigned int num_frames, size_t frame_size, void (*notify)(struct tegra_ivc *ivc, void *data), void *data); diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index d186bccd125d..aadb845d281d 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h @@ -118,9 +118,9 @@ enum tegra_io_pad { TEGRA_IO_PAD_PEX_CLK_2, TEGRA_IO_PAD_PEX_CNTRL, TEGRA_IO_PAD_PEX_CTL2, - TEGRA_IO_PAD_PEX_L0_RST_N, - TEGRA_IO_PAD_PEX_L1_RST_N, - TEGRA_IO_PAD_PEX_L5_RST_N, + TEGRA_IO_PAD_PEX_L0_RST, + TEGRA_IO_PAD_PEX_L1_RST, + TEGRA_IO_PAD_PEX_L5_RST, TEGRA_IO_PAD_PWR_CTL, TEGRA_IO_PAD_SDMMC1, TEGRA_IO_PAD_SDMMC1_HV, |