diff options
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/rk3399-cru.h | 6 | ||||
| -rw-r--r-- | include/dt-bindings/firmware/imx/rsrc.h | 302 | ||||
| -rw-r--r-- | include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 90 |
3 files changed, 252 insertions, 146 deletions
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 44e0a319f077..39169d94a44e 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -547,8 +547,8 @@ #define SRST_H_PERILP0 171 #define SRST_H_PERILP0_NOC 172 #define SRST_ROM 173 -#define SRST_CRYPTO_S 174 -#define SRST_CRYPTO_M 175 +#define SRST_CRYPTO0_S 174 +#define SRST_CRYPTO0_M 175 /* cru_softrst_con11 */ #define SRST_P_DCF 176 @@ -556,7 +556,7 @@ #define SRST_CM0S 178 #define SRST_CM0S_DBG 179 #define SRST_CM0S_PO 180 -#define SRST_CRYPTO 181 +#define SRST_CRYPTO0 181 #define SRST_P_PERILP1_SGRF 182 #define SRST_P_PERILP1_GRF 183 #define SRST_CRYPTO1_S 184 diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h index 1675de05ad33..1a8c025d77b8 100644 --- a/include/dt-bindings/firmware/imx/rsrc.h +++ b/include/dt-bindings/firmware/imx/rsrc.h @@ -13,30 +13,30 @@ * never be changed or removed (only added to at the end of the list). */ -#define IMX_SC_R_A53 0 -#define IMX_SC_R_A53_0 1 -#define IMX_SC_R_A53_1 2 -#define IMX_SC_R_A53_2 3 -#define IMX_SC_R_A53_3 4 -#define IMX_SC_R_A72 5 -#define IMX_SC_R_A72_0 6 -#define IMX_SC_R_A72_1 7 -#define IMX_SC_R_A72_2 8 -#define IMX_SC_R_A72_3 9 +#define IMX_SC_R_AP_0 0 +#define IMX_SC_R_AP_0_0 1 +#define IMX_SC_R_AP_0_1 2 +#define IMX_SC_R_AP_0_2 3 +#define IMX_SC_R_AP_0_3 4 +#define IMX_SC_R_AP_1 5 +#define IMX_SC_R_AP_1_0 6 +#define IMX_SC_R_AP_1_1 7 +#define IMX_SC_R_AP_1_2 8 +#define IMX_SC_R_AP_1_3 9 #define IMX_SC_R_CCI 10 #define IMX_SC_R_DB 11 #define IMX_SC_R_DRC_0 12 #define IMX_SC_R_DRC_1 13 #define IMX_SC_R_GIC_SMMU 14 -#define IMX_SC_R_IRQSTR_M4_0 15 -#define IMX_SC_R_IRQSTR_M4_1 16 -#define IMX_SC_R_SMMU 17 -#define IMX_SC_R_GIC 18 +#define IMX_SC_R_IRQSTR_MCU_0 15 +#define IMX_SC_R_IRQSTR_MCU_1 16 +#define IMX_SC_R_SMMU_0 17 +#define IMX_SC_R_GIC_0 18 #define IMX_SC_R_DC_0_BLIT0 19 #define IMX_SC_R_DC_0_BLIT1 20 #define IMX_SC_R_DC_0_BLIT2 21 #define IMX_SC_R_DC_0_BLIT_OUT 22 -#define IMX_SC_R_PERF 23 +#define IMX_SC_R_PERF_0 23 #define IMX_SC_R_USB_1_PHY 24 #define IMX_SC_R_DC_0_WARP 25 #define IMX_SC_R_V2X_MU_0 26 @@ -56,11 +56,14 @@ #define IMX_SC_R_V2X_MU_3 40 #define IMX_SC_R_V2X_MU_4 41 #define IMX_SC_R_DC_1_WARP 42 +#define IMX_SC_R_STM 43 #define IMX_SC_R_SECVIO 44 #define IMX_SC_R_DC_1_VIDEO0 45 #define IMX_SC_R_DC_1_VIDEO1 46 #define IMX_SC_R_DC_1_FRAC0 47 +#define IMX_SC_R_V2X 48 #define IMX_SC_R_DC_1 49 +#define IMX_SC_R_UNUSED14 50 #define IMX_SC_R_DC_1_PLL_0 51 #define IMX_SC_R_DC_1_PLL_1 52 #define IMX_SC_R_SPI_0 53 @@ -151,10 +154,10 @@ #define IMX_SC_R_DMA_1_CH29 137 #define IMX_SC_R_DMA_1_CH30 138 #define IMX_SC_R_DMA_1_CH31 139 -#define IMX_SC_R_UNUSED1 140 -#define IMX_SC_R_UNUSED2 141 -#define IMX_SC_R_UNUSED3 142 -#define IMX_SC_R_UNUSED4 143 +#define IMX_SC_R_V2X_PID0 140 +#define IMX_SC_R_V2X_PID1 141 +#define IMX_SC_R_V2X_PID2 142 +#define IMX_SC_R_V2X_PID3 143 #define IMX_SC_R_GPU_0_PID0 144 #define IMX_SC_R_GPU_0_PID1 145 #define IMX_SC_R_GPU_0_PID2 146 @@ -183,7 +186,7 @@ #define IMX_SC_R_PCIE_B 169 #define IMX_SC_R_SATA_0 170 #define IMX_SC_R_SERDES_1 171 -#define IMX_SC_R_HSIO_GPIO 172 +#define IMX_SC_R_HSIO_GPIO_0 172 #define IMX_SC_R_MATCH_15 173 #define IMX_SC_R_MATCH_16 174 #define IMX_SC_R_MATCH_17 175 @@ -250,15 +253,15 @@ #define IMX_SC_R_ROM_0 236 #define IMX_SC_R_FSPI_0 237 #define IMX_SC_R_FSPI_1 238 -#define IMX_SC_R_IEE 239 -#define IMX_SC_R_IEE_R0 240 -#define IMX_SC_R_IEE_R1 241 -#define IMX_SC_R_IEE_R2 242 -#define IMX_SC_R_IEE_R3 243 -#define IMX_SC_R_IEE_R4 244 -#define IMX_SC_R_IEE_R5 245 -#define IMX_SC_R_IEE_R6 246 -#define IMX_SC_R_IEE_R7 247 +#define IMX_SC_R_IEE_0 239 +#define IMX_SC_R_IEE_0_R0 240 +#define IMX_SC_R_IEE_0_R1 241 +#define IMX_SC_R_IEE_0_R2 242 +#define IMX_SC_R_IEE_0_R3 243 +#define IMX_SC_R_IEE_0_R4 244 +#define IMX_SC_R_IEE_0_R5 245 +#define IMX_SC_R_IEE_0_R6 246 +#define IMX_SC_R_IEE_0_R7 247 #define IMX_SC_R_SDHC_0 248 #define IMX_SC_R_SDHC_1 249 #define IMX_SC_R_SDHC_2 250 @@ -289,46 +292,50 @@ #define IMX_SC_R_LVDS_2_PWM_0 275 #define IMX_SC_R_LVDS_2_I2C_0 276 #define IMX_SC_R_LVDS_2_I2C_1 277 -#define IMX_SC_R_M4_0_PID0 278 -#define IMX_SC_R_M4_0_PID1 279 -#define IMX_SC_R_M4_0_PID2 280 -#define IMX_SC_R_M4_0_PID3 281 -#define IMX_SC_R_M4_0_PID4 282 -#define IMX_SC_R_M4_0_RGPIO 283 -#define IMX_SC_R_M4_0_SEMA42 284 -#define IMX_SC_R_M4_0_TPM 285 -#define IMX_SC_R_M4_0_PIT 286 -#define IMX_SC_R_M4_0_UART 287 -#define IMX_SC_R_M4_0_I2C 288 -#define IMX_SC_R_M4_0_INTMUX 289 -#define IMX_SC_R_M4_0_MU_0B 292 -#define IMX_SC_R_M4_0_MU_0A0 293 -#define IMX_SC_R_M4_0_MU_0A1 294 -#define IMX_SC_R_M4_0_MU_0A2 295 -#define IMX_SC_R_M4_0_MU_0A3 296 -#define IMX_SC_R_M4_0_MU_1A 297 -#define IMX_SC_R_M4_1_PID0 298 -#define IMX_SC_R_M4_1_PID1 299 -#define IMX_SC_R_M4_1_PID2 300 -#define IMX_SC_R_M4_1_PID3 301 -#define IMX_SC_R_M4_1_PID4 302 -#define IMX_SC_R_M4_1_RGPIO 303 -#define IMX_SC_R_M4_1_SEMA42 304 -#define IMX_SC_R_M4_1_TPM 305 -#define IMX_SC_R_M4_1_PIT 306 -#define IMX_SC_R_M4_1_UART 307 -#define IMX_SC_R_M4_1_I2C 308 -#define IMX_SC_R_M4_1_INTMUX 309 -#define IMX_SC_R_M4_1_MU_0B 312 -#define IMX_SC_R_M4_1_MU_0A0 313 -#define IMX_SC_R_M4_1_MU_0A1 314 -#define IMX_SC_R_M4_1_MU_0A2 315 -#define IMX_SC_R_M4_1_MU_0A3 316 -#define IMX_SC_R_M4_1_MU_1A 317 +#define IMX_SC_R_MCU_0_PID0 278 +#define IMX_SC_R_MCU_0_PID1 279 +#define IMX_SC_R_MCU_0_PID2 280 +#define IMX_SC_R_MCU_0_PID3 281 +#define IMX_SC_R_MCU_0_PID4 282 +#define IMX_SC_R_MCU_0_RGPIO 283 +#define IMX_SC_R_MCU_0_SEMA42 284 +#define IMX_SC_R_MCU_0_TPM 285 +#define IMX_SC_R_MCU_0_PIT 286 +#define IMX_SC_R_MCU_0_UART 287 +#define IMX_SC_R_MCU_0_I2C 288 +#define IMX_SC_R_MCU_0_INTMUX 289 +#define IMX_SC_R_ENET_0_A0 290 +#define IMX_SC_R_ENET_0_A1 291 +#define IMX_SC_R_MCU_0_MU_0B 292 +#define IMX_SC_R_MCU_0_MU_0A0 293 +#define IMX_SC_R_MCU_0_MU_0A1 294 +#define IMX_SC_R_MCU_0_MU_0A2 295 +#define IMX_SC_R_MCU_0_MU_0A3 296 +#define IMX_SC_R_MCU_0_MU_1A 297 +#define IMX_SC_R_MCU_1_PID0 298 +#define IMX_SC_R_MCU_1_PID1 299 +#define IMX_SC_R_MCU_1_PID2 300 +#define IMX_SC_R_MCU_1_PID3 301 +#define IMX_SC_R_MCU_1_PID4 302 +#define IMX_SC_R_MCU_1_RGPIO 303 +#define IMX_SC_R_MCU_1_SEMA42 304 +#define IMX_SC_R_MCU_1_TPM 305 +#define IMX_SC_R_MCU_1_PIT 306 +#define IMX_SC_R_MCU_1_UART 307 +#define IMX_SC_R_MCU_1_I2C 308 +#define IMX_SC_R_MCU_1_INTMUX 309 +#define IMX_SC_R_UNUSED17 310 +#define IMX_SC_R_UNUSED18 311 +#define IMX_SC_R_MCU_1_MU_0B 312 +#define IMX_SC_R_MCU_1_MU_0A0 313 +#define IMX_SC_R_MCU_1_MU_0A1 314 +#define IMX_SC_R_MCU_1_MU_0A2 315 +#define IMX_SC_R_MCU_1_MU_0A3 316 +#define IMX_SC_R_MCU_1_MU_1A 317 #define IMX_SC_R_SAI_0 318 #define IMX_SC_R_SAI_1 319 #define IMX_SC_R_SAI_2 320 -#define IMX_SC_R_IRQSTR_SCU2 321 +#define IMX_SC_R_IRQSTR_AP_0 321 #define IMX_SC_R_IRQSTR_DSP 322 #define IMX_SC_R_ELCDIF_PLL 323 #define IMX_SC_R_OCRAM 324 @@ -373,33 +380,33 @@ #define IMX_SC_R_VPU_PID5 363 #define IMX_SC_R_VPU_PID6 364 #define IMX_SC_R_VPU_PID7 365 -#define IMX_SC_R_VPU_UART 366 -#define IMX_SC_R_VPUCORE 367 -#define IMX_SC_R_VPUCORE_0 368 -#define IMX_SC_R_VPUCORE_1 369 -#define IMX_SC_R_VPUCORE_2 370 -#define IMX_SC_R_VPUCORE_3 371 +#define IMX_SC_R_ENET_0_A2 366 +#define IMX_SC_R_ENET_1_A0 367 +#define IMX_SC_R_ENET_1_A1 368 +#define IMX_SC_R_ENET_1_A2 369 +#define IMX_SC_R_ENET_1_A3 370 +#define IMX_SC_R_ENET_1_A4 371 #define IMX_SC_R_DMA_4_CH0 372 #define IMX_SC_R_DMA_4_CH1 373 #define IMX_SC_R_DMA_4_CH2 374 #define IMX_SC_R_DMA_4_CH3 375 #define IMX_SC_R_DMA_4_CH4 376 -#define IMX_SC_R_ISI_CH0 377 -#define IMX_SC_R_ISI_CH1 378 -#define IMX_SC_R_ISI_CH2 379 -#define IMX_SC_R_ISI_CH3 380 -#define IMX_SC_R_ISI_CH4 381 -#define IMX_SC_R_ISI_CH5 382 -#define IMX_SC_R_ISI_CH6 383 -#define IMX_SC_R_ISI_CH7 384 -#define IMX_SC_R_MJPEG_DEC_S0 385 -#define IMX_SC_R_MJPEG_DEC_S1 386 -#define IMX_SC_R_MJPEG_DEC_S2 387 -#define IMX_SC_R_MJPEG_DEC_S3 388 -#define IMX_SC_R_MJPEG_ENC_S0 389 -#define IMX_SC_R_MJPEG_ENC_S1 390 -#define IMX_SC_R_MJPEG_ENC_S2 391 -#define IMX_SC_R_MJPEG_ENC_S3 392 +#define IMX_SC_R_ISI_0_CH0 377 +#define IMX_SC_R_ISI_0_CH1 378 +#define IMX_SC_R_ISI_0_CH2 379 +#define IMX_SC_R_ISI_0_CH3 380 +#define IMX_SC_R_ISI_0_CH4 381 +#define IMX_SC_R_ISI_0_CH5 382 +#define IMX_SC_R_ISI_0_CH6 383 +#define IMX_SC_R_ISI_0_CH7 384 +#define IMX_SC_R_MJPEG_0_DEC_S0 385 +#define IMX_SC_R_MJPEG_0_DEC_S1 386 +#define IMX_SC_R_MJPEG_0_DEC_S2 387 +#define IMX_SC_R_MJPEG_0_DEC_S3 388 +#define IMX_SC_R_MJPEG_0_ENC_S0 389 +#define IMX_SC_R_MJPEG_0_ENC_S1 390 +#define IMX_SC_R_MJPEG_0_ENC_S2 391 +#define IMX_SC_R_MJPEG_0_ENC_S3 392 #define IMX_SC_R_MIPI_0 393 #define IMX_SC_R_MIPI_0_PWM_0 394 #define IMX_SC_R_MIPI_0_I2C_0 395 @@ -514,11 +521,11 @@ #define IMX_SC_R_SECO_MU_3 504 #define IMX_SC_R_SECO_MU_4 505 #define IMX_SC_R_HDMI_RX_PWM_0 506 -#define IMX_SC_R_A35 507 -#define IMX_SC_R_A35_0 508 -#define IMX_SC_R_A35_1 509 -#define IMX_SC_R_A35_2 510 -#define IMX_SC_R_A35_3 511 +#define IMX_SC_R_AP_2 507 +#define IMX_SC_R_AP_2_0 508 +#define IMX_SC_R_AP_2_1 509 +#define IMX_SC_R_AP_2_2 510 +#define IMX_SC_R_AP_2_3 511 #define IMX_SC_R_DSP 512 #define IMX_SC_R_DSP_RAM 513 #define IMX_SC_R_CAAM_JR1_OUT 514 @@ -539,8 +546,8 @@ #define IMX_SC_R_BOARD_R5 529 #define IMX_SC_R_BOARD_R6 530 #define IMX_SC_R_BOARD_R7 531 -#define IMX_SC_R_MJPEG_DEC_MP 532 -#define IMX_SC_R_MJPEG_ENC_MP 533 +#define IMX_SC_R_MJPEG_0_DEC_MP 532 +#define IMX_SC_R_MJPEG_0_ENC_MP 533 #define IMX_SC_R_VPU_TS_0 534 #define IMX_SC_R_VPU_MU_0 535 #define IMX_SC_R_VPU_MU_1 536 @@ -573,6 +580,105 @@ #define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ /* + * Compatibility defines for sc_rsrc_t + */ +#define IMX_SC_R_A35 IMX_SC_R_AP_2 +#define IMX_SC_R_A35_0 IMX_SC_R_AP_2_0 +#define IMX_SC_R_A35_1 IMX_SC_R_AP_2_1 +#define IMX_SC_R_A35_2 IMX_SC_R_AP_2_2 +#define IMX_SC_R_A35_3 IMX_SC_R_AP_2_3 +#define IMX_SC_R_A53 IMX_SC_R_AP_0 +#define IMX_SC_R_A53_0 IMX_SC_R_AP_0_0 +#define IMX_SC_R_A53_1 IMX_SC_R_AP_0_1 +#define IMX_SC_R_A53_2 IMX_SC_R_AP_0_2 +#define IMX_SC_R_A53_3 IMX_SC_R_AP_0_3 +#define IMX_SC_R_A72 IMX_SC_R_AP_1 +#define IMX_SC_R_A72_0 IMX_SC_R_AP_1_0 +#define IMX_SC_R_A72_1 IMX_SC_R_AP_1_1 +#define IMX_SC_R_A72_2 IMX_SC_R_AP_1_2 +#define IMX_SC_R_A72_3 IMX_SC_R_AP_1_3 +#define IMX_SC_R_GIC IMX_SC_R_GIC_0 +#define IMX_SC_R_HSIO_GPIO IMX_SC_R_HSIO_GPIO_0 +#define IMX_SC_R_IEE IMX_SC_R_IEE_0 +#define IMX_SC_R_IEE_R0 IMX_SC_R_IEE_0_R0 +#define IMX_SC_R_IEE_R1 IMX_SC_R_IEE_0_R1 +#define IMX_SC_R_IEE_R2 IMX_SC_R_IEE_0_R2 +#define IMX_SC_R_IEE_R3 IMX_SC_R_IEE_0_R3 +#define IMX_SC_R_IEE_R4 IMX_SC_R_IEE_0_R4 +#define IMX_SC_R_IEE_R5 IMX_SC_R_IEE_0_R5 +#define IMX_SC_R_IEE_R6 IMX_SC_R_IEE_0_R6 +#define IMX_SC_R_IEE_R7 IMX_SC_R_IEE_0_R7 +#define IMX_SC_R_IRQSTR_M4_0 IMX_SC_R_IRQSTR_MCU_0 +#define IMX_SC_R_IRQSTR_M4_1 IMX_SC_R_IRQSTR_MCU_1 +#define IMX_SC_R_IRQSTR_SCU2 IMX_SC_R_IRQSTR_AP_0 +#define IMX_SC_R_ISI_CH0 IMX_SC_R_ISI_0_CH0 +#define IMX_SC_R_ISI_CH1 IMX_SC_R_ISI_0_CH1 +#define IMX_SC_R_ISI_CH2 IMX_SC_R_ISI_0_CH2 +#define IMX_SC_R_ISI_CH3 IMX_SC_R_ISI_0_CH3 +#define IMX_SC_R_ISI_CH4 IMX_SC_R_ISI_0_CH4 +#define IMX_SC_R_ISI_CH5 IMX_SC_R_ISI_0_CH5 +#define IMX_SC_R_ISI_CH6 IMX_SC_R_ISI_0_CH6 +#define IMX_SC_R_ISI_CH7 IMX_SC_R_ISI_0_CH7 +#define IMX_SC_R_M4_0_I2C IMX_SC_R_MCU_0_I2C +#define IMX_SC_R_M4_0_INTMUX IMX_SC_R_MCU_0_INTMUX +#define IMX_SC_R_M4_0_MU_0A0 IMX_SC_R_MCU_0_MU_0A0 +#define IMX_SC_R_M4_0_MU_0A1 IMX_SC_R_MCU_0_MU_0A1 +#define IMX_SC_R_M4_0_MU_0A2 IMX_SC_R_MCU_0_MU_0A2 +#define IMX_SC_R_M4_0_MU_0A3 IMX_SC_R_MCU_0_MU_0A3 +#define IMX_SC_R_M4_0_MU_0B IMX_SC_R_MCU_0_MU_0B +#define IMX_SC_R_M4_0_MU_1A IMX_SC_R_MCU_0_MU_1A +#define IMX_SC_R_M4_0_PID0 IMX_SC_R_MCU_0_PID0 +#define IMX_SC_R_M4_0_PID1 IMX_SC_R_MCU_0_PID1 +#define IMX_SC_R_M4_0_PID2 IMX_SC_R_MCU_0_PID2 +#define IMX_SC_R_M4_0_PID3 IMX_SC_R_MCU_0_PID3 +#define IMX_SC_R_M4_0_PID4 IMX_SC_R_MCU_0_PID4 +#define IMX_SC_R_M4_0_PIT IMX_SC_R_MCU_0_PIT +#define IMX_SC_R_M4_0_RGPIO IMX_SC_R_MCU_0_RGPIO +#define IMX_SC_R_M4_0_SEMA42 IMX_SC_R_MCU_0_SEMA42 +#define IMX_SC_R_M4_0_TPM IMX_SC_R_MCU_0_TPM +#define IMX_SC_R_M4_0_UART IMX_SC_R_MCU_0_UART +#define IMX_SC_R_M4_1_I2C IMX_SC_R_MCU_1_I2C +#define IMX_SC_R_M4_1_INTMUX IMX_SC_R_MCU_1_INTMUX +#define IMX_SC_R_M4_1_MU_0A0 IMX_SC_R_MCU_1_MU_0A0 +#define IMX_SC_R_M4_1_MU_0A1 IMX_SC_R_MCU_1_MU_0A1 +#define IMX_SC_R_M4_1_MU_0A2 IMX_SC_R_MCU_1_MU_0A2 +#define IMX_SC_R_M4_1_MU_0A3 IMX_SC_R_MCU_1_MU_0A3 +#define IMX_SC_R_M4_1_MU_0B IMX_SC_R_MCU_1_MU_0B +#define IMX_SC_R_M4_1_MU_1A IMX_SC_R_MCU_1_MU_1A +#define IMX_SC_R_M4_1_PID0 IMX_SC_R_MCU_1_PID0 +#define IMX_SC_R_M4_1_PID1 IMX_SC_R_MCU_1_PID1 +#define IMX_SC_R_M4_1_PID2 IMX_SC_R_MCU_1_PID2 +#define IMX_SC_R_M4_1_PID3 IMX_SC_R_MCU_1_PID3 +#define IMX_SC_R_M4_1_PID4 IMX_SC_R_MCU_1_PID4 +#define IMX_SC_R_M4_1_PIT IMX_SC_R_MCU_1_PIT +#define IMX_SC_R_M4_1_RGPIO IMX_SC_R_MCU_1_RGPIO +#define IMX_SC_R_M4_1_SEMA42 IMX_SC_R_MCU_1_SEMA42 +#define IMX_SC_R_M4_1_TPM IMX_SC_R_MCU_1_TPM +#define IMX_SC_R_M4_1_UART IMX_SC_R_MCU_1_UART +#define IMX_SC_R_MJPEG_DEC_MP IMX_SC_R_MJPEG_0_DEC_MP +#define IMX_SC_R_MJPEG_DEC_S0 IMX_SC_R_MJPEG_0_DEC_S0 +#define IMX_SC_R_MJPEG_DEC_S1 IMX_SC_R_MJPEG_0_DEC_S1 +#define IMX_SC_R_MJPEG_DEC_S2 IMX_SC_R_MJPEG_0_DEC_S2 +#define IMX_SC_R_MJPEG_DEC_S3 IMX_SC_R_MJPEG_0_DEC_S3 +#define IMX_SC_R_MJPEG_ENC_MP IMX_SC_R_MJPEG_0_ENC_MP +#define IMX_SC_R_MJPEG_ENC_S0 IMX_SC_R_MJPEG_0_ENC_S0 +#define IMX_SC_R_MJPEG_ENC_S1 IMX_SC_R_MJPEG_0_ENC_S1 +#define IMX_SC_R_MJPEG_ENC_S2 IMX_SC_R_MJPEG_0_ENC_S2 +#define IMX_SC_R_MJPEG_ENC_S3 IMX_SC_R_MJPEG_0_ENC_S3 +#define IMX_SC_R_PERF IMX_SC_R_PERF_0 +#define IMX_SC_R_SMMU IMX_SC_R_SMMU_0 +#define IMX_SC_R_VPU_UART IMX_SC_R_ENET_0_A2 +#define IMX_SC_R_VPUCORE IMX_SC_R_ENET_1_A0 +#define IMX_SC_R_VPUCORE_0 IMX_SC_R_ENET_1_A1 +#define IMX_SC_R_VPUCORE_1 IMX_SC_R_ENET_1_A2 +#define IMX_SC_R_VPUCORE_2 IMX_SC_R_ENET_1_A3 +#define IMX_SC_R_VPUCORE_3 IMX_SC_R_ENET_1_A4 +#define IMX_SC_R_UNUSED1 IMX_SC_R_V2X_PID0 +#define IMX_SC_R_UNUSED2 IMX_SC_R_V2X_PID1 +#define IMX_SC_R_UNUSED3 IMX_SC_R_V2X_PID2 +#define IMX_SC_R_UNUSED4 IMX_SC_R_V2X_PID3 + +/* * Defines for SC CONTROL */ #define IMX_SC_C_TEMP 0 @@ -637,6 +743,10 @@ #define IMX_SC_C_INTF_SEL 59 #define IMX_SC_C_RXC_DLY 60 #define IMX_SC_C_TIMER_SEL 61 -#define IMX_SC_C_LAST 62 +#define IMX_SC_C_MISC0 62 +#define IMX_SC_C_MISC1 63 +#define IMX_SC_C_MISC2 64 +#define IMX_SC_C_MISC3 65 +#define IMX_SC_C_LAST 66 #endif /* __DT_BINDINGS_RSCRC_IMX_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h index 9426f27a1946..09fd169ad18e 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h @@ -6,62 +6,58 @@ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H #define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H -#ifndef PM8350_SID -#define PM8350_SID 1 -#endif - /* ADC channels for PM8350_ADC for PMIC7 */ -#define PM8350_ADC7_REF_GND (PM8350_SID << 8 | 0x0) -#define PM8350_ADC7_1P25VREF (PM8350_SID << 8 | 0x01) -#define PM8350_ADC7_VREF_VADC (PM8350_SID << 8 | 0x02) -#define PM8350_ADC7_DIE_TEMP (PM8350_SID << 8 | 0x03) - -#define PM8350_ADC7_AMUX_THM1 (PM8350_SID << 8 | 0x04) -#define PM8350_ADC7_AMUX_THM2 (PM8350_SID << 8 | 0x05) -#define PM8350_ADC7_AMUX_THM3 (PM8350_SID << 8 | 0x06) -#define PM8350_ADC7_AMUX_THM4 (PM8350_SID << 8 | 0x07) -#define PM8350_ADC7_AMUX_THM5 (PM8350_SID << 8 | 0x08) -#define PM8350_ADC7_GPIO1 (PM8350_SID << 8 | 0x0a) -#define PM8350_ADC7_GPIO2 (PM8350_SID << 8 | 0x0b) -#define PM8350_ADC7_GPIO3 (PM8350_SID << 8 | 0x0c) -#define PM8350_ADC7_GPIO4 (PM8350_SID << 8 | 0x0d) +#define PM8350_ADC7_REF_GND(sid) ((sid) << 8 | 0x0) +#define PM8350_ADC7_1P25VREF(sid) ((sid) << 8 | 0x01) +#define PM8350_ADC7_VREF_VADC(sid) ((sid) << 8 | 0x02) +#define PM8350_ADC7_DIE_TEMP(sid) ((sid) << 8 | 0x03) + +#define PM8350_ADC7_AMUX_THM1(sid) ((sid) << 8 | 0x04) +#define PM8350_ADC7_AMUX_THM2(sid) ((sid) << 8 | 0x05) +#define PM8350_ADC7_AMUX_THM3(sid) ((sid) << 8 | 0x06) +#define PM8350_ADC7_AMUX_THM4(sid) ((sid) << 8 | 0x07) +#define PM8350_ADC7_AMUX_THM5(sid) ((sid) << 8 | 0x08) +#define PM8350_ADC7_GPIO1(sid) ((sid) << 8 | 0x0a) +#define PM8350_ADC7_GPIO2(sid) ((sid) << 8 | 0x0b) +#define PM8350_ADC7_GPIO3(sid) ((sid) << 8 | 0x0c) +#define PM8350_ADC7_GPIO4(sid) ((sid) << 8 | 0x0d) /* 30k pull-up1 */ -#define PM8350_ADC7_AMUX_THM1_30K_PU (PM8350_SID << 8 | 0x24) -#define PM8350_ADC7_AMUX_THM2_30K_PU (PM8350_SID << 8 | 0x25) -#define PM8350_ADC7_AMUX_THM3_30K_PU (PM8350_SID << 8 | 0x26) -#define PM8350_ADC7_AMUX_THM4_30K_PU (PM8350_SID << 8 | 0x27) -#define PM8350_ADC7_AMUX_THM5_30K_PU (PM8350_SID << 8 | 0x28) -#define PM8350_ADC7_GPIO1_30K_PU (PM8350_SID << 8 | 0x2a) -#define PM8350_ADC7_GPIO2_30K_PU (PM8350_SID << 8 | 0x2b) -#define PM8350_ADC7_GPIO3_30K_PU (PM8350_SID << 8 | 0x2c) -#define PM8350_ADC7_GPIO4_30K_PU (PM8350_SID << 8 | 0x2d) +#define PM8350_ADC7_AMUX_THM1_30K_PU(sid) ((sid) << 8 | 0x24) +#define PM8350_ADC7_AMUX_THM2_30K_PU(sid) ((sid) << 8 | 0x25) +#define PM8350_ADC7_AMUX_THM3_30K_PU(sid) ((sid) << 8 | 0x26) +#define PM8350_ADC7_AMUX_THM4_30K_PU(sid) ((sid) << 8 | 0x27) +#define PM8350_ADC7_AMUX_THM5_30K_PU(sid) ((sid) << 8 | 0x28) +#define PM8350_ADC7_GPIO1_30K_PU(sid) ((sid) << 8 | 0x2a) +#define PM8350_ADC7_GPIO2_30K_PU(sid) ((sid) << 8 | 0x2b) +#define PM8350_ADC7_GPIO3_30K_PU(sid) ((sid) << 8 | 0x2c) +#define PM8350_ADC7_GPIO4_30K_PU(sid) ((sid) << 8 | 0x2d) /* 100k pull-up2 */ -#define PM8350_ADC7_AMUX_THM1_100K_PU (PM8350_SID << 8 | 0x44) -#define PM8350_ADC7_AMUX_THM2_100K_PU (PM8350_SID << 8 | 0x45) -#define PM8350_ADC7_AMUX_THM3_100K_PU (PM8350_SID << 8 | 0x46) -#define PM8350_ADC7_AMUX_THM4_100K_PU (PM8350_SID << 8 | 0x47) -#define PM8350_ADC7_AMUX_THM5_100K_PU (PM8350_SID << 8 | 0x48) -#define PM8350_ADC7_GPIO1_100K_PU (PM8350_SID << 8 | 0x4a) -#define PM8350_ADC7_GPIO2_100K_PU (PM8350_SID << 8 | 0x4b) -#define PM8350_ADC7_GPIO3_100K_PU (PM8350_SID << 8 | 0x4c) -#define PM8350_ADC7_GPIO4_100K_PU (PM8350_SID << 8 | 0x4d) +#define PM8350_ADC7_AMUX_THM1_100K_PU(sid) ((sid) << 8 | 0x44) +#define PM8350_ADC7_AMUX_THM2_100K_PU(sid) ((sid) << 8 | 0x45) +#define PM8350_ADC7_AMUX_THM3_100K_PU(sid) ((sid) << 8 | 0x46) +#define PM8350_ADC7_AMUX_THM4_100K_PU(sid) ((sid) << 8 | 0x47) +#define PM8350_ADC7_AMUX_THM5_100K_PU(sid) ((sid) << 8 | 0x48) +#define PM8350_ADC7_GPIO1_100K_PU(sid) ((sid) << 8 | 0x4a) +#define PM8350_ADC7_GPIO2_100K_PU(sid) ((sid) << 8 | 0x4b) +#define PM8350_ADC7_GPIO3_100K_PU(sid) ((sid) << 8 | 0x4c) +#define PM8350_ADC7_GPIO4_100K_PU(sid) ((sid) << 8 | 0x4d) /* 400k pull-up3 */ -#define PM8350_ADC7_AMUX_THM1_400K_PU (PM8350_SID << 8 | 0x64) -#define PM8350_ADC7_AMUX_THM2_400K_PU (PM8350_SID << 8 | 0x65) -#define PM8350_ADC7_AMUX_THM3_400K_PU (PM8350_SID << 8 | 0x66) -#define PM8350_ADC7_AMUX_THM4_400K_PU (PM8350_SID << 8 | 0x67) -#define PM8350_ADC7_AMUX_THM5_400K_PU (PM8350_SID << 8 | 0x68) -#define PM8350_ADC7_GPIO1_400K_PU (PM8350_SID << 8 | 0x6a) -#define PM8350_ADC7_GPIO2_400K_PU (PM8350_SID << 8 | 0x6b) -#define PM8350_ADC7_GPIO3_400K_PU (PM8350_SID << 8 | 0x6c) -#define PM8350_ADC7_GPIO4_400K_PU (PM8350_SID << 8 | 0x6d) +#define PM8350_ADC7_AMUX_THM1_400K_PU(sid) ((sid) << 8 | 0x64) +#define PM8350_ADC7_AMUX_THM2_400K_PU(sid) ((sid) << 8 | 0x65) +#define PM8350_ADC7_AMUX_THM3_400K_PU(sid) ((sid) << 8 | 0x66) +#define PM8350_ADC7_AMUX_THM4_400K_PU(sid) ((sid) << 8 | 0x67) +#define PM8350_ADC7_AMUX_THM5_400K_PU(sid) ((sid) << 8 | 0x68) +#define PM8350_ADC7_GPIO1_400K_PU(sid) ((sid) << 8 | 0x6a) +#define PM8350_ADC7_GPIO2_400K_PU(sid) ((sid) << 8 | 0x6b) +#define PM8350_ADC7_GPIO3_400K_PU(sid) ((sid) << 8 | 0x6c) +#define PM8350_ADC7_GPIO4_400K_PU(sid) ((sid) << 8 | 0x6d) /* 1/3 Divider */ -#define PM8350_ADC7_GPIO4_DIV3 (PM8350_SID << 8 | 0x8d) +#define PM8350_ADC7_GPIO4_DIV3(sid) ((sid) << 8 | 0x8d) -#define PM8350_ADC7_VPH_PWR (PM8350_SID << 8 | 0x8e) +#define PM8350_ADC7_VPH_PWR(sid) ((sid) << 8 | 0x8e) #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ |