diff options
Diffstat (limited to 'arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 7a82896dcbf6..8fdd5f020425 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,65 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + eth2_rgmii_pins_a: eth2-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 8, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 9, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('C', 10, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('C', 4, AF10)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('F', 7, AF10)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('C', 6, AF10)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = <STM32_PINMUX('C', 5, AF10)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins4 { + pinmux = <STM32_PINMUX('G', 0, AF10)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 12, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('F', 9, AF10)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins5 { + pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 7, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 8, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('F', 8, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('C', 6, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 0, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('F', 9, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('C', 3, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('F', 6, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + i2c2_pins_a: i2c2-0 { pins { pinmux = <STM32_PINMUX('B', 5, AF9)>, /* I2C2_SCL */ @@ -128,6 +187,47 @@ <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */ }; }; + + usart6_pins_a: usart6-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 13, AF3)>, /* USART6_TX */ + <STM32_PINMUX('G', 5, AF3)>; /* USART6_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 14, AF3)>, /* USART6_RX */ + <STM32_PINMUX('F', 15, AF3)>; /* USART6_CTS_NSS */ + bias-pull-up; + }; + }; + + usart6_idle_pins_a: usart6-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */ + <STM32_PINMUX('F', 15, ANALOG)>; /* USART6_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('G', 5, AF3)>; /* USART6_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('F', 14, AF3)>; /* USART6_RX */ + bias-pull-up; + }; + }; + + usart6_sleep_pins_a: usart6-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */ + <STM32_PINMUX('G', 5, ANALOG)>, /* USART6_RTS */ + <STM32_PINMUX('F', 15, ANALOG)>, /* USART6_CTS_NSS */ + <STM32_PINMUX('F', 14, ANALOG)>; /* USART6_RX */ + }; + }; }; &pinctrl_z { |