diff options
Diffstat (limited to 'Documentation/devicetree')
154 files changed, 3042 insertions, 1030 deletions
diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml index 3292c669ee11..7c38c08dbf3f 100644 --- a/Documentation/devicetree/bindings/arm/airoha.yaml +++ b/Documentation/devicetree/bindings/arm/airoha.yaml @@ -22,6 +22,10 @@ properties: - enum: - airoha,en7523-evb - const: airoha,en7523 + - items: + - enum: + - airoha,en7581-evb + - const: airoha,en7581 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index a374b98080fe..0647851ae1f5 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -91,6 +91,7 @@ properties: - libretech,aml-s905x-cc - libretech,aml-s905x-cc-v2 - nexbox,a95x + - osmc,vero4k - const: amlogic,s905x - const: amlogic,meson-gxl @@ -107,6 +108,13 @@ properties: - const: amlogic,s905d - const: amlogic,meson-gxl + - description: Boards with the Amlogic Meson GXLX S905L SoC + items: + - enum: + - amlogic,p271 + - const: amlogic,s905l + - const: amlogic,meson-gxlx + - description: Boards with the Amlogic Meson GXM S912 SoC items: - enum: @@ -169,6 +177,8 @@ properties: - azw,gtking - azw,gtking-pro - bananapi,bpi-m2s + - dream,dreambox-one + - dream,dreambox-two - hardkernel,odroid-go-ultra - hardkernel,odroid-n2 - hardkernel,odroid-n2l diff --git a/Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml b/Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml new file mode 100644 index 000000000000..ce5f2e1ec1ea --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,juno-fpga-apb-regs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Juno FPGA APB Registers + +maintainers: + - Sudeep Holla <sudeep.holla@arm.com> + +properties: + compatible: + items: + - const: arm,juno-fpga-apb-regs + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +patternProperties: + "^led@[0-9a-f]+,[0-9a-f]$": + $ref: /schemas/leds/register-bit-led.yaml# + +required: + - compatible + - reg + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + syscon@10000 { + compatible = "arm,juno-fpga-apb-regs", "syscon", "simple-mfd"; + reg = <0x010000 0x1000>; + ranges = <0x0 0x10000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + led@8,0 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x01>; + label = "vexpress:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index 162a39dab218..e4ff71f006b8 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -23,6 +23,12 @@ properties: - raspberrypi,4-model-b - const: brcm,bcm2711 + - description: BCM2712 based Boards + items: + - enum: + - raspberrypi,5-model-b + - const: brcm,bcm2712 + - description: BCM2835 based Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6d185d09cb6a..80747d79418a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -8,7 +8,6 @@ title: Freescale i.MX Platforms maintainers: - Shawn Guo <shawnguo@kernel.org> - - Li Yang <leoyang.li@nxp.com> properties: $nodename: @@ -363,6 +362,12 @@ properties: - const: gw,ventana - const: fsl,imx6q + - description: i.MX6Q Kontron SMARC-sAMX6i on SMARC Eval Carrier 2.0 + items: + - const: kontron,imx6q-samx6i-ads2 + - const: kontron,imx6q-samx6i + - const: fsl,imx6q + - description: i.MX6Q PHYTEC phyBOARD-Mira items: - enum: @@ -544,6 +549,12 @@ properties: - const: gw,ventana - const: fsl,imx6dl + - description: i.MX6DL Kontron SMARC-sAMX6i on SMARC Eval Carrier 2.0 + items: + - const: kontron,imx6dl-samx6i-ads2 + - const: kontron,imx6dl-samx6i + - const: fsl,imx6dl + - description: i.MX6DL PHYTEC phyBOARD-Mira items: - enum: @@ -946,6 +957,13 @@ properties: - prt,prt8mm # i.MX8MM Protonic PRT8MM Board - const: fsl,imx8mm + - description: Compulab i.MX8MM UCM SoM based boards + items: + - enum: + - compulab,imx8mm-iot-gateway # i.MX8MM Compulab IoT-Gateway + - const: compulab,imx8mm-ucm-som # i.MX8MM Compulab UCM SoM + - const: fsl,imx8mm + - description: Emtop i.MX8MM based Boards items: - const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1 @@ -1145,8 +1163,9 @@ properties: version as an industrial computing device. items: - enum: - - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL - - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM + - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL + - tq,imx8mp-tqma8mpql-mba8mp-ras314 # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MP-RAS314 + - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM - const: fsl,imx8mp - description: i.MX8MQ based Boards @@ -1272,9 +1291,16 @@ properties: - description: i.MX93 based Boards items: - enum: + - fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 + - description: i.MX95 based Boards + items: + - enum: + - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board + - const: fsl,imx95 + - description: i.MXRT1050 based Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml index 7f06b1080244..25a2b42105e5 100644 --- a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml +++ b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml @@ -20,7 +20,7 @@ description: | initialized early into boot process and provides services to Operating Systems on multiple processors including ones running Linux. - See http://processors.wiki.ti.com/index.php/TISCI for protocol definition. + See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition. The TI-SCI node describes the Texas Instrument's System Controller entity node. This parent node may optionally have additional children nodes which describe diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml index 16d2e132d3d1..538d91be8857 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml @@ -82,4 +82,22 @@ properties: - const: marvell,armada-ap807-quad - const: marvell,armada-ap807 + - description: + SolidRun CN9130 SoM based single-board computers + items: + - enum: + - solidrun,cn9130-clearfog-base + - solidrun,cn9130-clearfog-pro + - solidrun,cn9131-solidwan + - const: solidrun,cn9130-sr-som + - const: marvell,cn9130 + + - description: + SolidRun CN9132 COM-Express Type 7 based single-board computers + items: + - enum: + - solidrun,cn9132-clearfog + - const: solidrun,cn9132-sr-cex7 + - const: marvell,cn9130 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 09f9ffd3ff7b..1d4bb50fcd8d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -85,12 +85,15 @@ properties: - const: mediatek,mt7629 - items: - enum: + - cudy,wr3000-v1 + - openwrt,one - xiaomi,ax3000t - const: mediatek,mt7981b - items: - enum: - acelink,ew-7886cax - bananapi,bpi-r3 + - bananapi,bpi-r3mini - mediatek,mt7986a-rfb - const: mediatek,mt7986a - items: @@ -293,6 +296,13 @@ properties: - const: google,tentacruel-sku327683 - const: google,tentacruel - const: mediatek,mt8186 + - description: Google Voltorb (Acer Chromebook 311 C723/C732T) + items: + - enum: + - google,voltorb-sku589824 + - google,voltorb-sku589825 + - const: google,voltorb + - const: mediatek,mt8186 - items: - enum: - mediatek,mt8186-evb @@ -342,6 +352,14 @@ properties: - const: google,tomato-rev3 - const: google,tomato - const: mediatek,mt8195 + - description: HP Dojo sku1, 3, 5, 7 (HP Chromebook x360 13b-ca0002sa) + items: + - const: google,dojo-sku7 + - const: google,dojo-sku5 + - const: google,dojo-sku3 + - const: google,dojo-sku1 + - const: google,dojo + - const: mediatek,mt8195 - items: - enum: - mediatek,mt8195-demo @@ -353,6 +371,12 @@ properties: - const: mediatek,mt8365 - items: - enum: + - mediatek,mt8390-evk + - const: mediatek,mt8390 + - const: mediatek,mt8188 + - items: + - enum: + - kontron,3-5-sbc-i1200 - mediatek,mt8395-evk - radxa,nio-12l - const: mediatek,mt8395 diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index 99b5e9530707..528544d0a161 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -53,14 +53,20 @@ properties: - arm,cortex-a710-pmu - arm,cortex-a715-pmu - arm,cortex-a720-pmu + - arm,cortex-a725-pmu - arm,cortex-x1-pmu - arm,cortex-x2-pmu - arm,cortex-x3-pmu - arm,cortex-x4-pmu + - arm,cortex-x925-pmu - arm,neoverse-e1-pmu - arm,neoverse-n1-pmu - arm,neoverse-n2-pmu + - arm,neoverse-n3-pmu - arm,neoverse-v1-pmu + - arm,neoverse-v2-pmu + - arm,neoverse-v3-pmu + - arm,neoverse-v3ae-pmu - brcm,vulcan-pmu - cavium,thunder-pmu - nvidia,denver-pmu diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ae885414b181..f08e13b61172 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -42,6 +42,7 @@ description: | msm8996 msm8998 qcs404 + qcs8550 qcm2290 qcm6490 qdu1000 @@ -96,6 +97,7 @@ properties: - items: - enum: - qcom,apq8016-sbc + - schneider,apq8016-hmibsc - const: qcom,apq8016 - items: @@ -104,6 +106,7 @@ properties: - huawei,sturgeon - lg,lenok - samsung,matisse-wifi + - samsung,milletwifi - const: qcom,apq8026 - items: @@ -138,6 +141,7 @@ properties: - microsoft,makepeace - microsoft,moneypenny - motorola,falcon + - samsung,ms013g - samsung,s3ve3g - const: qcom,msm8226 @@ -175,6 +179,7 @@ properties: - items: - enum: - lge,hammerhead + - samsung,hlte - sony,xperia-amami - sony,xperia-honami - const: qcom,msm8974 @@ -182,8 +187,10 @@ properties: - items: - enum: - fairphone,fp2 + - htc,m8 - oneplus,bacon - samsung,klte + - sony,xperia-aries - sony,xperia-castor - sony,xperia-leo - const: qcom,msm8974pro @@ -203,8 +210,13 @@ properties: - asus,z00l - gplus,fl8005a - huawei,g7 + - lg,c50 + - lg,m216 - longcheer,l8910 - longcheer,l8150 + - motorola,harpia + - motorola,osprey + - motorola,surnia - qcom,msm8916-mtp - samsung,a3u-eur - samsung,a5u-eur @@ -316,6 +328,7 @@ properties: - items: - enum: - qcom,ipq5018-rdp432-c2 + - tplink,archer-ax55-v1 - const: qcom,ipq5018 - items: @@ -366,6 +379,7 @@ properties: - fairphone,fp5 - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 + - shift,otter - const: qcom,qcm6490 - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform @@ -802,6 +816,7 @@ properties: - items: - enum: + - lenovo,tbx605f - motorola,ali - const: qcom,sdm450 @@ -883,6 +898,7 @@ properties: - items: - enum: - qcom,sa8775p-ride + - qcom,sa8775p-ride-r3 - const: qcom,sa8775p - items: @@ -1004,17 +1020,28 @@ properties: - qcom,sm8550-hdk - qcom,sm8550-mtp - qcom,sm8550-qrd + - samsung,q5q - sony,pdx234 - const: qcom,sm8550 - items: - enum: + - qcom,qcs8550-aim300-aiot + - const: qcom,qcs8550-aim300 + - const: qcom,qcs8550 + - const: qcom,sm8550 + + - items: + - enum: + - qcom,sm8650-hdk - qcom,sm8650-mtp - qcom,sm8650-qrd - const: qcom,sm8650 - items: - enum: + - asus,vivobook-s15 + - lenovo,yoga-slim7x - qcom,x1e80100-crd - qcom,x1e80100-qcp - const: qcom,x1e80100 diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index e04c213a0dee..1ef09fbfdfaf 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -248,6 +248,13 @@ properties: - const: friendlyarm,nanopc-t6 - const: rockchip,rk3588 + - description: FriendlyElec CM3588-based boards + items: + - enum: + - friendlyarm,cm3588-nas + - const: friendlyarm,cm3588 + - const: rockchip,rk3588 + - description: GameForce Chi items: - const: gameforce,chi @@ -627,6 +634,11 @@ properties: - const: mqmaker,miqi - const: rockchip,rk3288 + - description: Neardi LBA3368 + items: + - const: neardi,lba3368 + - const: rockchip,rk3368 + - description: Netxeon R89 board items: - const: netxeon,r89 @@ -799,11 +811,21 @@ properties: - const: radxa,rock3a - const: rockchip,rk3568 + - description: Radxa ROCK 3B + items: + - const: radxa,rock-3b + - const: rockchip,rk3568 + - description: Radxa ROCK 3C items: - const: radxa,rock-3c - const: rockchip,rk3566 + - description: Radxa ROCK 5 ITX + items: + - const: radxa,rock-5-itx + - const: rockchip,rk3588 + - description: Radxa ROCK 5A items: - const: radxa,rock-5a @@ -814,6 +836,18 @@ properties: - const: radxa,rock-5b - const: rockchip,rk3588 + - description: Radxa ROCK S0 + items: + - const: radxa,rock-s0 + - const: rockchip,rk3308 + + - description: Radxa ZERO 3W/3E + items: + - enum: + - radxa,zero-3e + - radxa,zero-3w + - const: rockchip,rk3566 + - description: Rikomagic MK808 v1 items: - const: rikomagic,mk808 @@ -959,6 +993,14 @@ properties: - const: wolfvision,rk3568-pf5 - const: rockchip,rk3568 + - description: Xunlong Orange Pi 3B + items: + - enum: + - xunlong,orangepi-3b-v1.1 + - xunlong,orangepi-3b-v2.1 + - const: xunlong,orangepi-3b + - const: rockchip,rk3566 + - description: Xunlong Orange Pi 5 Plus items: - const: xunlong,orangepi-5-plus diff --git a/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt deleted file mode 100644 index 3b8fbf3c00c5..000000000000 --- a/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt +++ /dev/null @@ -1,19 +0,0 @@ -ARM Dual Cluster System Configuration Block -------------------------------------------- - -The Dual Cluster System Configuration Block (DCSCB) provides basic -functionality for controlling clocks, resets and configuration pins in -the Dual Cluster System implemented by the Real-Time System Model (RTSM). - -Required properties: - -- compatible : should be "arm,rtsm,dcscb" - -- reg : physical base address and the size of the registers window - -Example: - - dcscb@60000000 { - compatible = "arm,rtsm,dcscb"; - reg = <0x60000000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml index d2dce238ff5d..3e996346b264 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml @@ -54,11 +54,10 @@ unevaluatedProperties: false examples: - | - mlahb: ahb@38000000 { + ahb { compatible = "st,mlahb", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - reg = <0x10000000 0x40000>; ranges; dma-ranges = <0x00000000 0x38000000 0x10000>, <0x10000000 0x10000000 0x60000>, diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index bc2f43330ae4..58099949e8f3 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -59,6 +59,12 @@ properties: - prt,prtt1s # Protonic PRTT1S - const: st,stm32mp151 + - description: DH STM32MP135 DHCOR SoM based Boards + items: + - const: dh,stm32mp135f-dhcor-dhsbc + - const: dh,stm32mp135f-dhcor-som + - const: st,stm32mp135 + - description: DH STM32MP151 DHCOR SoM based Boards items: - const: dh,stm32mp151a-dhcor-testbench diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index c6d0d8d81ed4..09dc6f424986 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -57,17 +57,17 @@ properties: - const: allwinner,sun8i-v3s - description: Anbernic RG35XX (2024) - - items: + items: - const: anbernic,rg35xx-2024 - const: allwinner,sun50i-h700 - description: Anbernic RG35XX Plus - - items: + items: - const: anbernic,rg35xx-plus - const: allwinner,sun50i-h700 - description: Anbernic RG35XX H - - items: + items: - const: anbernic,rg35xx-h - const: allwinner,sun50i-h700 @@ -708,12 +708,12 @@ properties: - const: olimex,a64-teres-i - const: allwinner,sun50i-a64 - - description: Pine64 + - description: Pine64 PINE A64 items: - const: pine64,pine64 - const: allwinner,sun50i-a64 - - description: Pine64+ + - description: Pine64 PINE A64+ items: - const: pine64,pine64-plus - const: allwinner,sun50i-a64 @@ -724,17 +724,17 @@ properties: - const: sochip,s3 - const: allwinner,sun8i-v3 - - description: Pine64 PineH64 model A + - description: Pine64 PINE H64 Model A items: - const: pine64,pine-h64 - const: allwinner,sun50i-h6 - - description: Pine64 PineH64 model B + - description: Pine64 PINE H64 Model B items: - const: pine64,pine-h64-model-b - const: allwinner,sun50i-h6 - - description: Pine64 LTS + - description: Pine64 PINE A64 LTS items: - const: pine64,pine64-lts - const: allwinner,sun50i-r18 @@ -763,17 +763,17 @@ properties: - const: pine64,pinephone - const: allwinner,sun50i-a64 - - description: Pine64 PineTab, Development Sample + - description: Pine64 PineTab Developer Sample items: - const: pine64,pinetab - const: allwinner,sun50i-a64 - - description: Pine64 PineTab, Early Adopter's batch (and maybe later ones) + - description: Pine64 PineTab Early Adopter items: - const: pine64,pinetab-early-adopter - const: allwinner,sun50i-a64 - - description: Pine64 SoPine Baseboard + - description: Pine64 SOPINE items: - const: pine64,sopine-baseboard - const: pine64,sopine diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 52b51fd7044e..4d9c5fbb4c26 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -25,6 +25,12 @@ properties: - ti,am62a7-sk - const: ti,am62a7 + - description: K3 AM62A7 SoC PHYTEC phyBOARD-Lyra + items: + - const: phytec,am62a7-phyboard-lyra-rdk + - const: phytec,am62a-phycore-som + - const: ti,am62a7 + - description: K3 AM62P5 SoC and Boards items: - enum: diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 07ccbda4a0ab..68ea5f70b75f 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: - qcom,qdu1000-llcc + - qcom,sa8775p-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sc8180x-llcc @@ -66,7 +67,6 @@ allOf: compatible: contains: enum: - - qcom,qdu1000-llcc - qcom,sc7180-llcc - qcom,sm6350-llcc then: @@ -85,6 +85,33 @@ allOf: compatible: contains: enum: + - qcom,sa8775p-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: - qcom,sc7280-llcc then: properties: @@ -104,6 +131,7 @@ allOf: compatible: contains: enum: + - qcom,qdu1000-llcc - qcom,sc8180x-llcc - qcom,sc8280xp-llcc - qcom,x1e80100-llcc @@ -141,8 +169,31 @@ allOf: - qcom,sm8150-llcc - qcom,sm8250-llcc - qcom,sm8350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: - qcom,sm8450-llcc - qcom,sm8550-llcc + - qcom,sm8650-llcc then: properties: reg: @@ -151,7 +202,8 @@ allOf: - description: LLCC1 base register region - description: LLCC2 base register region - description: LLCC3 base register region - - description: LLCC broadcast base register region + - description: LLCC broadcast OR register region + - description: LLCC broadcast AND register region reg-names: items: - const: llcc0_base @@ -159,6 +211,7 @@ allOf: - const: llcc2_base - const: llcc3_base - const: llcc_broadcast_base + - const: llcc_broadcast_and_base additionalProperties: false diff --git a/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml new file mode 100644 index 000000000000..6d61098e388b --- /dev/null +++ b/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive StarLink Cache Controller + +maintainers: + - Joshua Yeong <joshua.yeong@starfivetech.com> + +description: + StarFive's StarLink Cache Controller manages the L3 cache shared between + clusters of CPU cores. The cache driver enables RISC-V non-standard cache + management as an alternative to instructions in the RISC-V Zicbom extension. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +# We need a select here so we don't match all nodes with 'cache' +select: + properties: + compatible: + contains: + enum: + - starfive,jh8100-starlink-cache + + required: + - compatible + +properties: + compatible: + items: + - const: starfive,jh8100-starlink-cache + - const: cache + + reg: + maxItems: 1 + +unevaluatedProperties: false + +required: + - compatible + - reg + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + cache-controller@15000000 { + compatible = "starfive,jh8100-starlink-cache", "cache"; + reg = <0x0 0x15000000 0x0 0x278>; + cache-block-size = <64>; + cache-level = <3>; + cache-sets = <8192>; + cache-size = <0x400000>; + cache-unified; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml index 944a0ea79cd6..824781cbdf34 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -33,6 +33,9 @@ properties: - description: PCIE30 PHY3 pipe clock source - description: USB3 PHY pipe clock source + '#interconnect-cells': + const: 1 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml new file mode 100644 index 000000000000..734880805c1b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on QCM2290 + +maintainers: + - Konrad Dybcio <konradybcio@kernel.org> + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,qcm2290-gpucc.h + +properties: + compatible: + const: qcom,qcm2290-gpucc + + reg: + maxItems: 1 + + clocks: + items: + - description: AHB interface clock, + - description: SoC CXO clock + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + power-domains: + description: + A phandle and PM domain specifier for the CX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required CX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-qcm2290.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,qcm2290-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd QCM2290_VDDCX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index fa0e5b6b02b8..f58edfc10f4c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -8,15 +8,17 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450 maintainers: - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> + - Jagadeesh Kona <quic_jkona@quicinc.com> description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SM8450. - See also:: + See also: + include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h - include/dt-bindings/clock/qcom,sc8280xp-camcc.h + include/dt-bindings/clock/qcom,sm8650-camcc.h include/dt-bindings/clock/qcom,x1e80100-camcc.h allOf: @@ -28,6 +30,7 @@ properties: - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8550-camcc + - qcom,sm8650-camcc - qcom,x1e80100-camcc clocks: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index bad8f019a8d3..8ce5972a65d5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -8,18 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450 maintainers: - Taniya Das <quic_tdas@quicinc.com> + - Jagadeesh Kona <quic_jkona@quicinc.com> description: | Qualcomm video clock control module provides the clocks, resets and power domains on SM8450. - See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h + See also: + include/dt-bindings/clock/qcom,sm8450-videocc.h + include/dt-bindings/clock/qcom,sm8650-videocc.h properties: compatible: enum: - qcom,sm8450-videocc - qcom,sm8550-videocc + - qcom,sm8650-videocc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml b/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml index 0a9d6a4c4b66..66e8e66ca175 100644 --- a/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml +++ b/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml @@ -36,7 +36,7 @@ properties: The second cell should contain the clock ID. - Please see http://processors.wiki.ti.com/index.php/TISCI for + Please see https://software-dl.ti.com/tisci/esd/latest/index.html for protocol documentation for the values to be used for different devices. additionalProperties: false diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml index acfb4b2ee7a9..d54140f18d34 100644 --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -59,8 +59,8 @@ properties: - 3 dma-channels: - minItems: 1 - maxItems: 64 + minimum: 1 + maximum: 64 clocks: minItems: 1 diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 7de2c29606e5..308af58180d1 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -72,14 +72,17 @@ properties: - const: tx - const: tx_reply - const: rx + - const: rx_reply minItems: 2 mboxes: description: List of phandle and mailbox channel specifiers. It should contain - exactly one, two or three mailboxes; the first one or two for transmitting - messages ("tx") and another optional ("rx") for receiving notifications - and delayed responses, if supported by the platform. + exactly one, two, three or four mailboxes; the first one or two for + transmitting messages ("tx") and another optional ("rx") for receiving + notifications and delayed responses, if supported by the platform. + The optional ("rx_reply") is for notifications completion interrupt, + if supported by the platform. The number of mailboxes needed for transmitting messages depends on the type of channels exposed by the specific underlying mailbox controller; one single channel descriptor is enough if such channel is bidirectional, @@ -92,9 +95,10 @@ properties: 2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels 2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels 3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels + 4 mbox / 2 shmem => SCMI TX and RX over 4 mailbox unidirectional channels Any other combination of mboxes and shmem is invalid. minItems: 1 - maxItems: 3 + maxItems: 4 shmem: description: diff --git a/Documentation/devicetree/bindings/firmware/cznic,turris-omnia-mcu.yaml b/Documentation/devicetree/bindings/firmware/cznic,turris-omnia-mcu.yaml new file mode 100644 index 000000000000..af9249695ef5 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/cznic,turris-omnia-mcu.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CZ.NIC's Turris Omnia MCU + +maintainers: + - Marek Behún <kabel@kernel.org> + +description: + The MCU on Turris Omnia acts as a system controller providing additional + GPIOs, interrupts, watchdog, system power off and wakeup configuration. + +properties: + compatible: + const: cznic,turris-omnia-mcu + + reg: + description: MCU I2C slave address + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: | + The first cell specifies the interrupt number (0 to 63), the second cell + specifies interrupt type (which can be one of IRQ_TYPE_EDGE_RISING, + IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH). + The interrupt numbers correspond sequentially to GPIO numbers, taking the + GPIO banks into account: + IRQ number GPIO bank GPIO pin within bank + 0 - 15 0 0 - 15 + 16 - 47 1 0 - 31 + 48 - 63 2 0 - 15 + There are several exceptions: + IRQ number meaning + 11 LED panel brightness changed by button press + 13 TRNG entropy ready + 14 ECDSA message signature computation done + + gpio-controller: true + + '#gpio-cells': + const: 3 + description: + The first cell is bank number (0, 1 or 2), the second cell is pin number + within the bank (0 to 15 for banks 0 and 2, 0 to 31 for bank 1), and the + third cell specifies consumer flags. + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - gpio-controller + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + system-controller@2a { + compatible = "cznic,turris-omnia-mcu"; + reg = <0x2a>; + + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_NONE>; + + gpio-controller; + #gpio-cells = <3>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 47d3d2d52acd..2cc83771d8e7 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -93,6 +93,11 @@ properties: protocol to handle sleeping SCM calls. maxItems: 1 + memory-region: + description: + Phandle to the memory region reserved for the shared memory bridge to TZ. + maxItems: 1 + qcom,sdi-enabled: description: Indicates that the SDI (Secure Debug Image) has been enabled by TZ @@ -193,6 +198,16 @@ allOf: then: properties: interrupts: false + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,scm-sa8775p + then: + properties: + memory-region: false required: - compatible diff --git a/Documentation/devicetree/bindings/fuse/renesas,rcar-efuse.yaml b/Documentation/devicetree/bindings/fuse/renesas,rcar-efuse.yaml new file mode 100644 index 000000000000..d7e289244e72 --- /dev/null +++ b/Documentation/devicetree/bindings/fuse/renesas,rcar-efuse.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fuse/renesas,rcar-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: R-Car E-FUSE connected to PFC + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The E-FUSE is a type of non-volatile memory, which is accessible through the + Pin Function Controller (PFC) on some R-Car Gen4 SoCs. + +properties: + compatible: + enum: + - renesas,r8a779a0-efuse # R-Car V3U + - renesas,r8a779f0-efuse # R-Car S4-8 + + reg: + maxItems: 1 + description: PFC System Group Fuse Control and Monitor register block + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> + #include <dt-bindings/power/r8a779a0-sysc.h> + + fuse: fuse@e6078800 { + compatible = "renesas,r8a779a0-efuse"; + reg = <0xe6078800 0x100>; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + }; diff --git a/Documentation/devicetree/bindings/fuse/renesas,rcar-otp.yaml b/Documentation/devicetree/bindings/fuse/renesas,rcar-otp.yaml new file mode 100644 index 000000000000..d74872ae9ff3 --- /dev/null +++ b/Documentation/devicetree/bindings/fuse/renesas,rcar-otp.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fuse/renesas,rcar-otp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: R-Car E-FUSE connected to OTP_MEM + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The E-FUSE is a type of non-volatile memory, which is accessible through the + One-Time Programmable Memory (OTP_MEM) module on some R-Car Gen4 SoCs. + +properties: + compatible: + enum: + - renesas,r8a779g0-otp # R-CarV4H + - renesas,r8a779h0-otp # R-CarV4M + + reg: + items: + - description: OTP_MEM_0 + - description: OTP_MEM_1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + otp: otp@e61be000 { + compatible = "renesas,r8a779g0-otp"; + reg = <0xe61be000 0x1000>, <0xe61bf000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml index 46bb121360dc..1046f0331c09 100644 --- a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml +++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml @@ -33,6 +33,11 @@ properties: gpio-controller: true + # Each SGPIO is represented as a pair of input and output GPIOs + gpio-line-names: + minItems: 160 + maxItems: 256 + '#gpio-cells': const: 2 @@ -41,6 +46,9 @@ properties: interrupt-controller: true + '#interrupt-cells': + const: 2 + clocks: maxItems: 1 @@ -55,6 +63,7 @@ required: - '#gpio-cells' - interrupts - interrupt-controller + - '#interrupt-cells' - ngpios - clocks - bus-frequency @@ -72,6 +81,7 @@ examples: reg = <0x1e780200 0x0100>; clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; + #interrupt-cells = <2>; ngpios = <80>; bus-frequency = <12000000>; }; diff --git a/Documentation/devicetree/bindings/gpio/atmel,at91rm9200-gpio.yaml b/Documentation/devicetree/bindings/gpio/atmel,at91rm9200-gpio.yaml new file mode 100644 index 000000000000..3dd70933ed8e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/atmel,at91rm9200-gpio.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/atmel,at91rm9200-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip GPIO controller (PIO) + +maintainers: + - Manikandan Muralidharan <manikandan.m@microchip.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - atmel,at91sam9x5-gpio + - microchip,sam9x60-gpio + - const: atmel,at91rm9200-gpio + - items: + - enum: + - microchip,sam9x7-gpio + - const: microchip,sam9x60-gpio + - const: atmel,at91rm9200-gpio + - items: + - const: atmel,at91rm9200-gpio + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + gpio-controller: true + gpio-line-names: true + + "#gpio-cells": + const: 2 + + clocks: + maxItems: 1 + + "#gpio-lines": + description: + Number of gpio, 32 by default if absent + maxItems: 1 + default: 32 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - gpio-controller + - "#gpio-cells" + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/at91.h> + #include <dt-bindings/interrupt-controller/irq.h> + + gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; +... diff --git a/Documentation/devicetree/bindings/gpio/fsl,qoriq-gpio.yaml b/Documentation/devicetree/bindings/gpio/fsl,qoriq-gpio.yaml new file mode 100644 index 000000000000..84fd82291ee4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/fsl,qoriq-gpio.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/fsl,qoriq-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + oneOf: + - enum: + - fsl,mpc5121-gpio + - fsl,mpc5125-gpio + - fsl,mpc8349-gpio + - fsl,mpc8572-gpio + - fsl,mpc8610-gpio + - fsl,pq3-gpio + - items: + - enum: + - fsl,ls1021a-gpio + - fsl,ls1028a-gpio + - fsl,ls1043a-gpio + - fsl,ls1046a-gpio + - fsl,ls1088a-gpio + - fsl,ls2080a-gpio + - const: fsl,qoriq-gpio + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#gpio-cells": + const: 2 + + gpio-controller: true + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + gpio-line-names: + minItems: 1 + maxItems: 32 + + little-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: + GPIO registers are used as little endian. If not + present registers are used as big endian by default. + +required: + - compatible + - reg + - interrupts + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + gpio@1100 { + compatible = "fsl,mpc5125-gpio"; + reg = <0x1100 0x080>; + interrupts = <78 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + gpio@2300000 { + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; + reg = <0x2300000 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt deleted file mode 100644 index cd28e932bf50..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller - -Required properties: -- compatible : Should be "fsl,<soc>-gpio" - The following <soc>s are known to be supported: - mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq, - ls1021a, ls1043a, ls2080a, ls1028a, ls1088a. -- reg : Address and length of the register set for the device -- interrupts : Should be the port interrupt shared by all 32 pins. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - -Optional properties: -- little-endian : GPIO registers are used as little endian. If not - present registers are used as big endian by default. - -Example of gpio-controller node for a mpc5125 SoC: - -gpio0: gpio@1100 { - compatible = "fsl,mpc5125-gpio"; - #gpio-cells = <2>; - reg = <0x1100 0x080>; - interrupts = <78 0x8>; -}; - -Example of gpio-controller node for a ls2080a SoC: - -gpio0: gpio@2300000 { - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 36 0x4>; /* Level high type */ - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; - - -Example of gpio-controller node for a ls1028a/ls1088a SoC: - -gpio1: gpio@2300000 { - compatible = "fsl,ls1028a-gpio", "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml index 99febb8ea1b6..51e8390d6b32 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml @@ -66,6 +66,7 @@ properties: - ti,tca6408 - ti,tca6416 - ti,tca6424 + - ti,tca9535 - ti,tca9538 - ti,tca9539 - ti,tca9554 diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml index a27f92950257..cabda2eab4a2 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml @@ -51,6 +51,10 @@ properties: gpio-controller: true + gpio-line-names: + minItems: 1 + maxItems: 32 + clocks: items: - description: SoC GPIO clock diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt deleted file mode 100644 index a37bd9ae2730..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt +++ /dev/null @@ -1,16 +0,0 @@ -Zevio GPIO controller - -Required properties: -- compatible: Should be "lsi,zevio-gpio" -- reg: Address and length of the register set for the device -- #gpio-cells: Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). -- gpio-controller: Marks the device node as a GPIO controller. - -Example: - gpio: gpio@90000000 { - compatible = "lsi,zevio-gpio"; - reg = <0x90000000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt deleted file mode 100644 index 29416f9c3220..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Atmel GPIO controller (PIO) - -Required properties: -- compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5. -- reg: Should contain GPIO controller registers location and length -- interrupts: Should be the port interrupt shared by all the pins. -- #gpio-cells: Should be two. The first cell is the pin number and - the second cell is used to specify optional parameters to declare if the GPIO - is active high or low. See gpio.txt. -- gpio-controller: Marks the device node as a GPIO controller. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. The first cell is the pin number and the - second cell is used to specify irq type flags, see the two cell description - in interrupt-controller/interrupts.txt for details. - -optional properties: -- #gpio-lines: Number of gpio if absent 32. - - -Example: - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x100>; - interrupts = <2 4>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <19>; - interrupt-controller; - #interrupt-cells = <2>; - }; - diff --git a/Documentation/devicetree/bindings/gpio/lsi,zevio-gpio.yaml b/Documentation/devicetree/bindings/gpio/lsi,zevio-gpio.yaml new file mode 100644 index 000000000000..e9e201a489e5 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/lsi,zevio-gpio.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/lsi,zevio-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Zevio GPIO controller + +maintainers: + - Pratik Farkase <pratikfarkase94@gmail.com> + +properties: + compatible: + items: + - const: lsi,zevio-gpio + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#gpio-cells": + const: 2 + + gpio-controller: true + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + +unevaluatedProperties: false + +examples: + - | + gpio@90000000 { + compatible = "lsi,zevio-gpio"; + reg = <0x90000000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/hwmon/g762.txt b/Documentation/devicetree/bindings/hwmon/g762.txt deleted file mode 100644 index 6d154c4923de..000000000000 --- a/Documentation/devicetree/bindings/hwmon/g762.txt +++ /dev/null @@ -1,47 +0,0 @@ -GMT G762/G763 PWM Fan controller - -Required node properties: - - - "compatible": must be either "gmt,g762" or "gmt,g763" - - "reg": I2C bus address of the device - - "clocks": a fixed clock providing input clock frequency - on CLK pin of the chip. - -Optional properties: - - - "fan_startv": fan startup voltage. Accepted values are 0, 1, 2 and 3. - The higher the more. - - - "pwm_polarity": pwm polarity. Accepted values are 0 (positive duty) - and 1 (negative duty). - - - "fan_gear_mode": fan gear mode. Supported values are 0, 1 and 2. - -If an optional property is not set in .dts file, then current value is kept -unmodified (e.g. u-boot installed value). - -Additional information on operational parameters for the device is available -in Documentation/hwmon/g762.rst. A detailed datasheet for the device is available -at http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf. - -Example g762 node: - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - g762_clk: fixedclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - } - } - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk> - fan_gear_mode = <0>; /* chip default */ - fan_startv = <1>; /* chip default */ - pwm_polarity = <0>; /* chip default */ - }; diff --git a/Documentation/devicetree/bindings/hwmon/gmt,g762.yaml b/Documentation/devicetree/bindings/hwmon/gmt,g762.yaml new file mode 100644 index 000000000000..8e1bffd252e6 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/gmt,g762.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/gmt,g762.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GMT G761/G762/G763 PWM Fan controller + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +description: | + GMT G761/G762/G763 PWM Fan controller. + + G761 supports an internal-clock hence the clocks property is optional. + If not defined, internal-clock will be used. (31KHz is the clock of + the internal crystal oscillator) + + If an optional property is not set in DT, then current value is kept + unmodified (e.g. bootloader installed value). + + Additional information on operational parameters for the device is available + in Documentation/hwmon/g762.rst. A detailed datasheet for the device is available + at http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf. + +properties: + compatible: + enum: + - gmt,g761 + - gmt,g762 + - gmt,g763 + + reg: + maxItems: 1 + + clocks: + description: a fixed clock providing input clock frequency on CLK + pin of the chip. + maxItems: 1 + + fan_startv: + description: Fan startup voltage step + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + pwm_polarity: + description: PWM polarity (positive or negative duty) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + fan_gear_mode: + description: FAN gear mode. Configure High speed fan setting factor + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + enum: + - gmt,g762 + - gmt,g763 +then: + required: + - clocks + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + + g761@1e { + compatible = "gmt,g761"; + reg = <0x1e>; + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/maxim,max6639.yaml b/Documentation/devicetree/bindings/hwmon/maxim,max6639.yaml new file mode 100644 index 000000000000..4f5837a30773 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/maxim,max6639.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/hwmon/maxim,max6639.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim max6639 + +maintainers: + - Naresh Solanki <naresh.solanki@9elements.com> + +description: | + The MAX6639 is a 2-channel temperature monitor with dual, automatic, PWM + fan-speed controller. It monitors its own temperature and one external + diode-connected transistor or the temperatures of two external diode-connected + transistors, typically available in CPUs, FPGAs, or GPUs. + + Datasheets: + https://datasheets.maximintegrated.com/en/ds/MAX6639-MAX6639F.pdf + +properties: + compatible: + enum: + - maxim,max6639 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#pwm-cells': + const: 3 + +required: + - compatible + - reg + +patternProperties: + "^fan@[0-1]$": + type: object + description: + Represents the two fans and their specific configuration. + + $ref: fan-common.yaml# + + unevaluatedProperties: false + + properties: + reg: + description: + The fan number. + + required: + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + fan1: fan-controller@10 { + compatible = "maxim,max6639"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <3>; + + fan@0 { + reg = <0x0>; + pulses-per-revolution = <2>; + max-rpm = <4000>; + target-rpm = <1000>; + pwms = <&fan1 0 25000 0>; + }; + + fan@1 { + reg = <0x1>; + pulses-per-revolution = <2>; + max-rpm = <8000>; + pwms = <&fan1 1 25000 0>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml index df86c2c92037..6ae961732e6b 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -66,6 +66,14 @@ properties: description: phandle to the regulator that provides the VS supply typically in range from 2.7 V to 5.5 V. + ti,alert-polarity-active-high: + description: Alert pin is asserted based on the value of Alert polarity Bit + of Mask/Enable register. Default value is Normal (0 which maps to + active-low open collector). The other value is Inverted + (1 which maps to active-high open collector). Specify this property to set + the alert polarity to active-high. + $ref: /schemas/types.yaml#/definitions/flag + required: - compatible - reg @@ -88,5 +96,6 @@ examples: label = "vdd_3v0"; shunt-resistor = <1000>; vs-supply = <&vdd_3v0>; + ti,alert-polarity-active-high; }; }; diff --git a/Documentation/devicetree/bindings/hwmon/ti,tmp108.yaml b/Documentation/devicetree/bindings/hwmon/ti,tmp108.yaml index 8b5307c875ff..0ad10d43fac0 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,tmp108.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,tmp108.yaml @@ -9,6 +9,14 @@ title: TMP108 temperature sensor maintainers: - Krzysztof Kozlowski <krzk@kernel.org> +description: | + The TMP108 is a digital-output temperature sensor with a + dynamically-programmable limit window, and under- and overtemperature + alert functions. + + Datasheets: + https://www.ti.com/product/TMP108 + properties: compatible: enum: @@ -24,6 +32,9 @@ properties: "#thermal-sensor-cells": const: 0 + vcc-supply: + description: phandle to the regulator that provides the V+ supply + required: - compatible - reg @@ -45,6 +56,7 @@ examples: interrupts = <7 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&tmp_alrt>; + vcc-supply = <&supply>; #thermal-sensor-cells = <0>; }; }; diff --git a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml index b1c13bab2472..b2d19cfb87ad 100644 --- a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml @@ -77,7 +77,7 @@ required: - clocks allOf: - - $ref: i2c-controller.yaml + - $ref: /schemas/i2c/i2c-controller.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/i2c/google,cros-ec-i2c-tunnel.yaml b/Documentation/devicetree/bindings/i2c/google,cros-ec-i2c-tunnel.yaml index ab151c9db219..580003cdfff5 100644 --- a/Documentation/devicetree/bindings/i2c/google,cros-ec-i2c-tunnel.yaml +++ b/Documentation/devicetree/bindings/i2c/google,cros-ec-i2c-tunnel.yaml @@ -21,7 +21,7 @@ description: | google,cros-ec-spi or google,cros-ec-i2c. allOf: - - $ref: i2c-controller.yaml# + - $ref: /schemas/i2c/i2c-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml index 96340a05754c..8265d709094d 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -139,7 +139,7 @@ allOf: Voltage output range of the channel as <minimum, maximum> Required connections: Rfb1x for: 0 to 2.5 V; 0 to 3V; 0 to 5 V; - Rfb2x for: 0 to 10 V; 2.5 to 7.5V; -5 to 5 V; + Rfb2x for: 0 to 10 V; -2.5 to 7.5V; -5 to 5 V; oneOf: - items: - const: 0 diff --git a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml index c384bf0bb25d..6bdb8040be65 100644 --- a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml +++ b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml @@ -22,7 +22,9 @@ properties: - const: allwinner,sun8i-a83t-r-lradc - const: allwinner,sun50i-r329-lradc - items: - - const: allwinner,sun20i-d1-lradc + - enum: + - allwinner,sun50i-h616-lradc + - allwinner,sun20i-d1-lradc - const: allwinner,sun50i-r329-lradc reg: diff --git a/Documentation/devicetree/bindings/input/elan,ekth6915.yaml b/Documentation/devicetree/bindings/input/elan,ekth6915.yaml index dc4ac41f2441..a62916d07a08 100644 --- a/Documentation/devicetree/bindings/input/elan,ekth6915.yaml +++ b/Documentation/devicetree/bindings/input/elan,ekth6915.yaml @@ -18,9 +18,12 @@ allOf: properties: compatible: - enum: - - elan,ekth6915 - - ilitek,ili2901 + oneOf: + - items: + - enum: + - elan,ekth5015m + - const: elan,ekth6915 + - const: elan,ekth6915 reg: const: 0x10 @@ -33,6 +36,12 @@ properties: reset-gpios: description: Reset GPIO; not all touchscreens using eKTH6915 hook this up. + no-reset-on-power-off: + type: boolean + description: + Reset line is wired so that it can (and should) be left deasserted when + the power supply is off. + vcc33-supply: description: The 3.3V supply to the touchscreen. @@ -58,8 +67,8 @@ examples: #address-cells = <1>; #size-cells = <0>; - ap_ts: touchscreen@10 { - compatible = "elan,ekth6915"; + touchscreen@10 { + compatible = "elan,ekth5015m", "elan,ekth6915"; reg = <0x10>; interrupt-parent = <&tlmm>; diff --git a/Documentation/devicetree/bindings/input/ilitek,ili2901.yaml b/Documentation/devicetree/bindings/input/ilitek,ili2901.yaml new file mode 100644 index 000000000000..1abeec768d79 --- /dev/null +++ b/Documentation/devicetree/bindings/input/ilitek,ili2901.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/ilitek,ili2901.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ilitek ILI2901 touchscreen controller + +maintainers: + - Jiri Kosina <jkosina@suse.com> + +description: + Supports the Ilitek ILI2901 touchscreen controller. + This touchscreen controller uses the i2c-hid protocol with a reset GPIO. + +allOf: + - $ref: /schemas/input/touchscreen/touchscreen.yaml# + +properties: + compatible: + enum: + - ilitek,ili2901 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + panel: true + + reset-gpios: + maxItems: 1 + + vcc33-supply: true + + vccio-supply: true + +required: + - compatible + - reg + - interrupts + - vcc33-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili2901"; + reg = <0x41>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + vcc33-supply = <&pp3300_ts>; + }; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index 05067e197abe..2cd1f5590fd9 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -35,6 +35,7 @@ properties: - qcom,sm8250-cpu-bwmon - qcom,sm8550-cpu-bwmon - qcom,sm8650-cpu-bwmon + - qcom,x1e80100-cpu-bwmon - const: qcom,sdm845-bwmon # BWMON v4, unified register space - items: - enum: @@ -44,6 +45,7 @@ properties: - qcom,sm8250-llcc-bwmon - qcom,sm8550-llcc-bwmon - qcom,sm8650-llcc-bwmon + - qcom,x1e80100-llcc-bwmon - const: qcom,sc7280-llcc-bwmon - const: qcom,sc7280-llcc-bwmon # BWMON v5 - const: qcom,sdm845-llcc-bwmon # BWMON v5 @@ -72,7 +74,6 @@ required: - interconnects - interrupts - operating-points-v2 - - opp-table - reg additionalProperties: false diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.yaml index 887e565b9573..199b34fdbefc 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.yaml @@ -8,7 +8,6 @@ title: Freescale Layerscape External Interrupt Controller maintainers: - Shawn Guo <shawnguo@kernel.org> - - Li Yang <leoyang.li@nxp.com> description: | Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA, diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt deleted file mode 100644 index 5fc03134a999..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt +++ /dev/null @@ -1,38 +0,0 @@ -Marvell Armada 370, 375, 38x, XP Interrupt Controller ------------------------------------------------------ - -Required properties: -- compatible: Should be "marvell,mpic" -- interrupt-controller: Identifies the node as an interrupt controller. -- msi-controller: Identifies the node as an PCI Message Signaled - Interrupt controller. -- #interrupt-cells: The number of cells to define the interrupts. Should be 1. - The cell is the IRQ number - -- reg: Should contain PMIC registers location and length. First pair - for the main interrupt registers, second pair for the per-CPU - interrupt registers. For this last pair, to be compliant with SMP - support, the "virtual" must be use (For the record, these registers - automatically map to the interrupt controller registers of the - current CPU) - -Optional properties: - -- interrupts: If defined, then it indicates that this MPIC is - connected as a slave to another interrupt controller. This is - typically the case on Armada 375 and Armada 38x, where the MPIC is - connected as a slave to the Cortex-A9 GIC. The provided interrupt - indicate to which GIC interrupt the MPIC output is connected. - -Example: - - mpic: interrupt-controller@d0020000 { - compatible = "marvell,mpic"; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - reg = <0xd0020a00 0x1d0>, - <0xd0021070 0x58>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,mpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,mpic.yaml new file mode 100644 index 000000000000..616a41c87352 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,mpic.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller + +maintainers: + - Marek Behún <kabel@kernel.org> + +description: | + The top-level interrupt controller on Marvell Armada 370 and XP. On these + platforms it also provides inter-processor interrupts. + + On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC. + + Provides MSI handling for the PCIe controllers. + +properties: + compatible: + const: marvell,mpic + + reg: + items: + - description: main registers + - description: per-cpu registers + + interrupts: + items: + - description: | + Parent interrupt on platforms where MPIC is not the top-level + interrupt controller. + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + msi-controller: true + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - msi-controller + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + interrupt-controller@20a00 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + msi-controller; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml index 3be1db30bf41..d1c3421bee10 100644 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: FSL/NXP Integrated Flash Controller maintainers: - - Li Yang <leoyang.li@nxp.com> + - Shawn Guo <shawnguo@kernel.org> description: | NXP's integrated flash controller (IFC) is an advanced version of the diff --git a/Documentation/devicetree/bindings/mfd/ti,twl.yaml b/Documentation/devicetree/bindings/mfd/ti,twl.yaml index c2357fecb56c..e94b0fd7af0f 100644 --- a/Documentation/devicetree/bindings/mfd/ti,twl.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,twl.yaml @@ -22,6 +22,32 @@ allOf: contains: const: ti,twl4030 then: + patternProperties: + "^regulator-": + properties: + compatible: + enum: + - ti,twl4030-vaux1 + - ti,twl4030-vaux2 + - ti,twl4030-vaux3 + - ti,twl4030-vaux4 + - ti,twl4030-vmmc1 + - ti,twl4030-vmmc2 + - ti,twl4030-vpll1 + - ti,twl4030-vpll2 + - ti,twl4030-vsim + - ti,twl4030-vdac + - ti,twl4030-vintana2 + - ti,twl4030-vio + - ti,twl4030-vdd1 + - ti,twl4030-vdd2 + - ti,twl4030-vintana1 + - ti,twl4030-vintdig + - ti,twl4030-vusb1v5 + - ti,twl4030-vusb1v8 + - ti,twl4030-vusb3v1 + ti,retain-on-reset: false + properties: madc: type: object @@ -50,13 +76,34 @@ allOf: properties: compatible: const: ti,twl4030-wdt - - if: properties: compatible: contains: const: ti,twl6030 then: + patternProperties: + "^regulator-": + properties: + compatible: + enum: + - ti,twl6030-vaux1 + - ti,twl6030-vaux2 + - ti,twl6030-vaux3 + - ti,twl6030-vmmc + - ti,twl6030-vpp + - ti,twl6030-vusim + - ti,twl6030-vana + - ti,twl6030-vcxio + - ti,twl6030-vdac + - ti,twl6030-vusb + - ti,twl6030-v1v8 + - ti,twl6030-v2v1 + - ti,twl6030-vdd1 + - ti,twl6030-vdd2 + - ti,twl6030-vdd3 + regulator-initial-mode: false + properties: gpadc: type: object @@ -69,6 +116,25 @@ allOf: contains: const: ti,twl6032 then: + patternProperties: + "^regulator-": + properties: + compatible: + enum: + - ti,twl6032-ldo1 + - ti,twl6032-ldo2 + - ti,twl6032-ldo3 + - ti,twl6032-ldo4 + - ti,twl6032-ldo5 + - ti,twl6032-ldo6 + - ti,twl6032-ldo7 + - ti,twl6032-ldoln + - ti,twl6032-ldousb + - ti,twl6032-smps3 + - ti,twl6032-smps4 + - ti,twl6032-vio + regulator-initial-mode: false + properties: gpadc: type: object @@ -112,6 +178,27 @@ properties: interrupts: maxItems: 1 +patternProperties: + "^regulator-": + type: object + unevaluatedProperties: false + $ref: /schemas/regulator/regulator.yaml + properties: + compatible: true + regulator-initial-mode: + enum: + - 0x08 # Sleep mode, the nominal output voltage is maintained + # with low power consumption with low load current capability + - 0x0e # Active mode, the regulator can deliver its nominal output + # voltage with full-load current capability + ti,retain-on-reset: + description: + Does not turn off the supplies during warm + reset. Could be needed for VMMC, as TWL6030 + reset sequence for this signal does not comply + with the SD specification. + type: boolean + unevaluatedProperties: false required: @@ -131,9 +218,85 @@ examples: compatible = "ti,twl6030"; reg = <0x48>; interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */ + interrupt-parent = <&gic>; interrupt-controller; #interrupt-cells = <1>; - interrupt-parent = <&gic>; + + gpadc { + compatible = "ti,twl6030-gpadc"; + interrupts = <6>; + #io-channel-cells = <1>; + }; + + rtc { + compatible = "ti,twl4030-rtc"; + interrupts = <8>; + }; + + regulator-vaux1 { + compatible = "ti,twl6030-vaux1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + }; + + regulator-vmmc1 { + compatible = "ti,twl6030-vmmc"; + ti,retain-on-reset; + }; }; }; + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@48 { + compatible = "ti,twl4030"; + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + interrupt-controller; + #interrupt-cells = <1>; + + bci { + compatible = "ti,twl4030-bci"; + interrupts = <9>, <2>; + bci3v1-supply = <&vusb3v1>; + io-channels = <&twl_madc 11>; + io-channel-names = "vac"; + }; + + twl_madc: madc { + compatible = "ti,twl4030-madc"; + interrupts = <3>; + #io-channel-cells = <1>; + }; + + pwrbutton { + compatible = "ti,twl4030-pwrbutton"; + interrupts = <8>; + }; + + rtc { + compatible = "ti,twl4030-rtc"; + interrupts = <11>; + }; + + regulator-vaux1 { + compatible = "ti,twl4030-vaux1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0xe>; + }; + + vusb3v1: regulator-vusb3v1 { + compatible = "ti,twl4030-vusb3v1"; + }; + + watchdog { + compatible = "ti,twl4030-wdt"; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml index bc403ae9e5d9..57646575a13f 100644 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml @@ -51,6 +51,9 @@ properties: set when controller's internal DMA engine cannot access the DRAM memory, like on the G12A dedicated SDIO controller. + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index cbd3d6c6c77f..eee6be7a7867 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -20,6 +20,7 @@ properties: - const: brcm,sdhci-brcmstb - items: - enum: + - brcm,bcm2712-sdhci - brcm,bcm74165b0-sdhci - brcm,bcm7445-sdhci - brcm,bcm7425-sdhci diff --git a/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml new file mode 100644 index 000000000000..b86ffb53b18b --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/fsl,esdhc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Enhanced Secure Digital Host Controller (eSDHC) + +description: + The Enhanced Secure Digital Host Controller provides an interface + for MMC, SD, and SDIO types of memory cards. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + items: + - enum: + - fsl,mpc8536-esdhc + - fsl,mpc8378-esdhc + - fsl,p2020-esdhc + - fsl,p4080-esdhc + - fsl,t1040-esdhc + - fsl,t4240-esdhc + - fsl,ls1012a-esdhc + - fsl,ls1028a-esdhc + - fsl,ls1088a-esdhc + - fsl,ls1043a-esdhc + - fsl,ls1046a-esdhc + - fsl,ls2080a-esdhc + - const: fsl,esdhc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: specifies eSDHC base clock frequency. + + sdhci,wp-inverted: + $ref: /schemas/types.yaml#/definitions/flag + deprecated: true + description: + specifies that eSDHC controller reports + inverted write-protect state; New devices should use the generic + "wp-inverted" property. + + sdhci,1-bit-only: + $ref: /schemas/types.yaml#/definitions/flag + deprecated: true + description: + specifies that a controller can only handle + 1-bit data transfers. New devices should use the generic + "bus-width = <1>" property. + + sdhci,auto-cmd12: + $ref: /schemas/types.yaml#/definitions/flag + description: + specifies that a controller can only handle auto CMD12. + + voltage-ranges: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: specifies minimum slot voltage (mV). + - description: specifies maximum slot voltage (mV). + minItems: 1 + maxItems: 8 + + dma-coherent: true + + little-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: + If the host controller is little-endian mode, specify + this property. The default endian mode is big-endian. + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: sdhci-common.yaml# + +unevaluatedProperties: false + +examples: + - | + mmc@2e000 { + compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <42 0x8>; + interrupt-parent = <&ipic>; + /* Filled in by U-Boot */ + clock-frequency = <100000000>; + voltage-ranges = <3300 3300>; + }; diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt deleted file mode 100644 index edb8cadb9541..000000000000 --- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt +++ /dev/null @@ -1,52 +0,0 @@ -* Freescale Enhanced Secure Digital Host Controller (eSDHC) - -The Enhanced Secure Digital Host Controller provides an interface -for MMC, SD, and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the sdhci-esdhc driver. - -Required properties: - - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc". - Possible compatibles for PowerPC: - "fsl,mpc8536-esdhc" - "fsl,mpc8378-esdhc" - "fsl,p2020-esdhc" - "fsl,p4080-esdhc" - "fsl,t1040-esdhc" - "fsl,t4240-esdhc" - Possible compatibles for ARM: - "fsl,ls1012a-esdhc" - "fsl,ls1028a-esdhc" - "fsl,ls1088a-esdhc" - "fsl,ls1043a-esdhc" - "fsl,ls1046a-esdhc" - "fsl,ls2080a-esdhc" - - clock-frequency : specifies eSDHC base clock frequency. - -Optional properties: - - sdhci,wp-inverted : specifies that eSDHC controller reports - inverted write-protect state; New devices should use the generic - "wp-inverted" property. - - sdhci,1-bit-only : specifies that a controller can only handle - 1-bit data transfers. New devices should use the generic - "bus-width = <1>" property. - - sdhci,auto-cmd12: specifies that a controller can only handle auto - CMD12. - - voltage-ranges : two cells are required, first cell specifies minimum - slot voltage (mV), second cell specifies maximum slot voltage (mV). - Several ranges could be specified. - - little-endian : If the host controller is little-endian mode, specify - this property. The default endian mode is big-endian. - -Example: - -sdhci@2e000 { - compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; - reg = <0x2e000 0x1000>; - interrupts = <42 0x8>; - interrupt-parent = <&ipic>; - /* Filled in by U-Boot */ - clock-frequency = <0>; - voltage-ranges = <3300 3300>; -}; diff --git a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml index 36acc40c7d18..6e2cdac6a85d 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml @@ -27,17 +27,19 @@ properties: maxItems: 1 voltage-ranges: - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-matrix description: | Two cells are required, first cell specifies minimum slot voltage (mV), second cell specifies maximum slot voltage (mV). items: - - description: | - value for minimum slot voltage in mV - default: 3200 - - description: | - value for maximum slot voltage in mV - default: 3400 + items: + - description: | + value for minimum slot voltage in mV + default: 3200 + - description: | + value for maximum slot voltage in mV + default: 3400 + maxItems: 1 gpios: description: | diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index c24c537f62b1..11979b026d21 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -51,6 +51,7 @@ properties: - qcom,sdm845-sdhci - qcom,sdx55-sdhci - qcom,sdx65-sdhci + - qcom,sdx75-sdhci - qcom,sm6115-sdhci - qcom,sm6125-sdhci - qcom,sm6350-sdhci diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt deleted file mode 100644 index eb7eb1b529f0..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Spreadtrum SDHCI controller (sdhci-sprd) - -The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface -for MMC, SD and SDIO types of cards. - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-sprd driver. - -Required properties: -- compatible: Should contain "sprd,sdhci-r11". -- reg: physical base address of the controller and length. -- interrupts: Interrupts used by the SDHCI controller. -- clocks: Should contain phandle for the clock feeding the SDHCI controller -- clock-names: Should contain the following: - "sdio" - SDIO source clock (required) - "enable" - gate clock which used for enabling/disabling the device (required) - "2x_enable" - gate clock controlling the device for some special platforms (optional) - -Optional properties: -- assigned-clocks: the same with "sdio" clock -- assigned-clock-parents: the default parent of "sdio" clock -- pinctrl-names: should be "default", "state_uhs" -- pinctrl-0: should contain default/high speed pin control -- pinctrl-1: should contain uhs mode pin control - -PHY DLL delays are used to delay the data valid window, and align the window -to sampling clock. PHY DLL delays can be configured by following properties, -and each property contains 4 cells which are used to configure the clock data -write line delay value, clock read command line delay value, clock read data -positive edge delay value and clock read data negative edge delay value. -Each cell's delay value unit is cycle of the PHY clock. - -- sprd,phy-delay-legacy: Delay value for legacy timing. -- sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing. -- sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing. -- sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing. -- sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing. -- sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing. -- sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing. -- sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing. -- sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing. - -Examples: - -sdio0: sdio@20600000 { - compatible = "sprd,sdhci-r11"; - reg = <0 0x20600000 0 0x1000>; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - - clock-names = "sdio", "enable"; - clocks = <&ap_clk CLK_EMMC_2X>, - <&apahb_gate CLK_EMMC_EB>; - assigned-clocks = <&ap_clk CLK_EMMC_2X>; - assigned-clock-parents = <&rpll CLK_RPLL_390M>; - - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&sd0_pins_default>; - pinctrl-1 = <&sd0_pins_uhs>; - - sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>; - bus-width = <8>; - non-removable; - no-sdio; - no-sd; - cap-mmc-hw-reset; - status = "okay"; -}; diff --git a/Documentation/devicetree/bindings/mmc/sprd,sdhci-r11.yaml b/Documentation/devicetree/bindings/mmc/sprd,sdhci-r11.yaml new file mode 100644 index 000000000000..b08081bc018b --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sprd,sdhci-r11.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SDHCI controller + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +properties: + compatible: + const: sprd,sdhci-r11 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + items: + - description: SDIO source clock + - description: gate clock for enabling/disabling the device + - description: gate clock controlling the device for some special platforms (optional) + + clock-names: + minItems: 2 + items: + - const: sdio + - const: enable + - const: 2x_enable + + pinctrl-0: + description: default/high speed pin control + maxItems: 1 + + pinctrl-1: + description: UHS mode pin control + maxItems: 1 + + pinctrl-names: + minItems: 1 + items: + - const: default + - const: state_uhs + +patternProperties: + "^sprd,phy-delay-(legacy|mmc-(ddr52|highspeed|hs[24]00|hs400es)|sd-(highspeed|uhs-sdr(50|104)))$": + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: clock data write line delay value + - description: clock read command line delay value + - description: clock read data positive edge delay value + - description: clock read data negative edge delay value + description: + PHY DLL delays are used to delay the data valid window, and align + the window to the sampling clock. Each cell's delay value unit is + cycle of the PHY clock. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +allOf: + - $ref: sdhci-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/sprd,sc9860-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + mmc@50430000 { + compatible = "sprd,sdhci-r11"; + reg = <0x50430000 0x1000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&aon_prediv CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>, + <&aon_gate CLK_EMMC_2X_EN>; + clock-names = "sdio", "enable", "2x_enable"; + + pinctrl-0 = <&sd0_pins_default>; + pinctrl-1 = <&sd0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + bus-width = <8>; + cap-mmc-hw-reset; + mmc-hs400-enhanced-strobe; + mmc-hs400-1_8v; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + non-removable; + no-sdio; + no-sd; + + sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; + sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; + sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; + sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; + }; +... diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml index c80c880a9dab..60aaf30d68ed 100644 --- a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml +++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml @@ -128,7 +128,6 @@ required: - cell-index - reg - fsl,fman-ports - - ptp-timer dependencies: pcs-handle-names: diff --git a/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml index 828439398fdf..fd4244fceced 100644 --- a/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml +++ b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml @@ -24,6 +24,7 @@ properties: managers: type: object + additionalProperties: false description: List of the PD69208T4/PD69204T4/PD69208M PSE managers. Each manager have 4 or 8 physical ports according to the chip version. No need to @@ -47,8 +48,9 @@ properties: - "#size-cells" patternProperties: - "^manager@0[0-9a-b]$": + "^manager@[0-9a-b]$": type: object + additionalProperties: false description: PD69208T4/PD69204T4/PD69208M PSE manager exposing 4 or 8 physical ports. @@ -69,9 +71,14 @@ properties: patternProperties: '^port@[0-7]$': type: object + additionalProperties: false + + properties: + reg: + maxItems: 1 + required: - reg - additionalProperties: false required: - reg diff --git a/Documentation/devicetree/bindings/net/pse-pd/ti,tps23881.yaml b/Documentation/devicetree/bindings/net/pse-pd/ti,tps23881.yaml index 4147adb11e10..6992d56832bf 100644 --- a/Documentation/devicetree/bindings/net/pse-pd/ti,tps23881.yaml +++ b/Documentation/devicetree/bindings/net/pse-pd/ti,tps23881.yaml @@ -29,13 +29,31 @@ properties: of the ports conversion matrix that establishes relationship between the logical ports and the physical channels. type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 patternProperties: '^channel@[0-7]$': type: object + additionalProperties: false + + properties: + reg: + maxItems: 1 + required: - reg + required: + - "#address-cells" + - "#size-cells" + unevaluatedProperties: false required: diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml index 6c96a4204e5d..37e8b98f2cdc 100644 --- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml @@ -30,6 +30,9 @@ properties: - items: - const: fsl,imx8dxl-ddr-pmu - const: fsl,imx8-ddr-pmu + - items: + - const: fsl,imx95-ddr-pmu + - const: fsl,imx93-ddr-pmu reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 50846a2d09c8..0bf2d9f093b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -29,7 +29,6 @@ properties: - qcom,pm7325-gpio - qcom,pm7550ba-gpio - qcom,pm8005-gpio - - qcom,pm8008-gpio - qcom,pm8018-gpio - qcom,pm8019-gpio - qcom,pm8038-gpio @@ -126,7 +125,6 @@ allOf: compatible: contains: enum: - - qcom,pm8008-gpio - qcom,pmi8950-gpio - qcom,pmr735d-gpio then: @@ -448,7 +446,6 @@ $defs: - gpio1-gpio10 for pm7325 - gpio1-gpio8 for pm7550ba - gpio1-gpio4 for pm8005 - - gpio1-gpio2 for pm8008 - gpio1-gpio6 for pm8018 - gpio1-gpio12 for pm8038 - gpio1-gpio40 for pm8058 diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml index dab3d92bc273..15d74138baa3 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml @@ -20,6 +20,8 @@ properties: enum: - amlogic,meson-a1-pwrc - amlogic,meson-s4-pwrc + - amlogic,a4-pwrc + - amlogic,a5-pwrc - amlogic,c3-pwrc - amlogic,t7-pwrc diff --git a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml new file mode 100644 index 000000000000..ec6115d3796b --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/adi,axi-pwmgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AXI PWM generator + +maintainers: + - Michael Hennerich <Michael.Hennerich@analog.com> + - Nuno Sá <nuno.sa@analog.com> + +description: + The Analog Devices AXI PWM generator can generate PWM signals + with variable pulse width and period. + + https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: adi,axi-pwmgen-2.00.a + + reg: + maxItems: 1 + + "#pwm-cells": + const: 2 + + clocks: + maxItems: 1 + +required: + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + pwm@44b00000 { + compatible = "adi,axi-pwmgen-2.00.a"; + reg = <0x44b00000 0x1000>; + clocks = <&spi_clk>; + #pwm-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml index 96cd6f3c3546..d20ad27657aa 100644 --- a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml @@ -23,7 +23,9 @@ properties: - atmel,sama5d2-pwm - microchip,sam9x60-pwm - items: - - const: microchip,sama7g5-pwm + - enum: + - microchip,sama7d65-pwm + - microchip,sama7g5-pwm - const: atmel,sama5d2-pwm - items: - const: microchip,sam9x7-pwm diff --git a/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml b/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml new file mode 100644 index 000000000000..7f9f72d95e7a --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/fsl,vf610-ftm-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale FlexTimer Module (FTM) PWM controller + +description: | + The same FTM PWM device can have a different endianness on different SoCs. The + device tree provides a property to describing this so that an operating system + device driver can handle all variants of the device. Refer to the table below + for the endianness of the FTM PWM block as integrated into the existing SoCs: + + SoC | FTM-PWM endianness + --------+------------------- + Vybrid | LE + LS1 | BE + LS2 | LE + + Please see ../regmap/regmap.txt for more detail about how to specify endian + modes in device tree. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + enum: + - fsl,vf610-ftm-pwm + - fsl,imx8qm-ftm-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: ftm_sys + - const: ftm_ext + - const: ftm_fix + - const: ftm_cnt_clk_en + + pinctrl-0: true + pinctrl-1: true + + pinctrl-names: + minItems: 1 + items: + - const: default + - const: sleep + + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: + Boolean property, required if the FTM PWM registers use a big- + endian rather than little-endian layout. + +required: + - compatible + - reg + - clocks + - clock-names + +allOf: + - $ref: pwm.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/vf610-clock.h> + + pwm@40038000 { + compatible = "fsl,vf610-ftm-pwm"; + reg = <0x40038000 0x1000>; + #pwm-cells = <3>; + clocks = <&clks VF610_CLK_FTM0>, + <&clks VF610_CLK_FTM0_EXT_SEL>, + <&clks VF610_CLK_FTM0_FIX_SEL>, + <&clks VF610_CLK_FTM0_EXT_FIX_EN>; + clock-names = "ftm_sys", "ftm_ext", "ftm_fix", "ftm_cnt_clk_en"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_1>; + big-endian; + }; diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml index a84a240a61dc..04148198e34d 100644 --- a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml @@ -68,7 +68,6 @@ required: - reg - clocks - clock-names - - interrupts additionalProperties: false diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt deleted file mode 100644 index 36532cd5ab25..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt +++ /dev/null @@ -1,55 +0,0 @@ -Freescale FlexTimer Module (FTM) PWM controller - -The same FTM PWM device can have a different endianness on different SoCs. The -device tree provides a property to describing this so that an operating system -device driver can handle all variants of the device. Refer to the table below -for the endianness of the FTM PWM block as integrated into the existing SoCs: - - SoC | FTM-PWM endianness - --------+------------------- - Vybrid | LE - LS1 | BE - LS2 | LE - -Please see ../regmap/regmap.txt for more detail about how to specify endian -modes in device tree. - - -Required properties: -- compatible : should be "fsl,<soc>-ftm-pwm" and one of the following - compatible strings: - - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610 - - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM -- reg: Physical base address and length of the controller's registers -- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of - the cells format. -- clock-names: Should include the following module clock source entries: - "ftm_sys" (module clock, also can be used as counter clock), - "ftm_ext" (external counter clock), - "ftm_fix" (fixed counter clock), - "ftm_cnt_clk_en" (external and fixed counter clock enable/disable). -- clocks: Must contain a phandle and clock specifier for each entry in - clock-names, please see clock/clock-bindings.txt for details of the property - values. -- pinctrl-names: Must contain a "default" entry. -- pinctrl-NNN: One property must exist for each entry in pinctrl-names. - See pinctrl/pinctrl-bindings.txt for details of the property values. -- big-endian: Boolean property, required if the FTM PWM registers use a big- - endian rather than little-endian layout. - -Example: - -pwm0: pwm@40038000 { - compatible = "fsl,vf610-ftm-pwm"; - reg = <0x40038000 0x1000>; - #pwm-cells = <3>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clks VF610_CLK_FTM0>, - <&clks VF610_CLK_FTM0_EXT_SEL>, - <&clks VF610_CLK_FTM0_FIX_SEL>, - <&clks VF610_CLK_FTM0_EXT_FIX_EN>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_1>; - big-endian; -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-gpio.yaml b/Documentation/devicetree/bindings/pwm/pwm-gpio.yaml new file mode 100644 index 000000000000..1576c193f2ab --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-gpio.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic software PWM for modulating GPIOs + +maintainers: + - Stefan Wahren <wahrenst@gmx.net> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: pwm-gpio + + "#pwm-cells": + const: 3 + description: + See pwm.yaml in this directory for a description of the cells format. + The first cell which represents the PWM instance number must always + be zero. + + gpios: + description: + GPIO to be modulated + maxItems: 1 + +required: + - compatible + - "#pwm-cells" + - gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + pwm { + #pwm-cells = <3>; + compatible = "pwm-gpio"; + gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/pwm/pwm.yaml b/Documentation/devicetree/bindings/pwm/pwm.yaml index abd9fa873354..f2206ec3c7c4 100644 --- a/Documentation/devicetree/bindings/pwm/pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm.yaml @@ -16,8 +16,10 @@ properties: pattern: "^pwm(@.*|-([0-9]|[1-9][0-9]+))?$" "#pwm-cells": - description: - Number of cells in a PWM specifier. + description: | + Number of cells in a PWM specifier. Typically the cells represent, in + order: the chip-relative PWM number, the PWM period in nanoseconds and + optionally a number of flags (defined in <dt-bindings/pwm/pwm.h>). required: - "#pwm-cells" diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml new file mode 100644 index 000000000000..704828687970 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6873-dvfsrc-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek DVFSRC-controlled Regulators + +description: + The Dynamic Voltage and Frequency Scaling Resource Collector Regulators + are controlled with votes to the DVFSRC hardware. + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +properties: + compatible: + enum: + - mediatek,mt6873-dvfsrc-regulator + - mediatek,mt8183-dvfsrc-regulator + - mediatek,mt8192-dvfsrc-regulator + - mediatek,mt8195-dvfsrc-regulator + + dvfsrc-vcore: + description: DVFSRC-controlled SoC Vcore regulator + $ref: regulator.yaml# + unevaluatedProperties: false + + dvfsrc-vscp: + description: DVFSRC-controlled System Control Processor regulator + $ref: regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + +anyOf: + - required: + - dvfsrc-vcore + - required: + - dvfsrc-vscp + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml index 6317daf76d1f..cd4aa27218a1 100644 --- a/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml @@ -16,7 +16,11 @@ description: | properties: compatible: - const: mediatek,mt6315-regulator + oneOf: + - items: + - const: mediatek,mt6319-regulator + - const: mediatek,mt6315-regulator + - const: mediatek,mt6315-regulator reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml b/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml index 849bfa50bdba..f8057bba747a 100644 --- a/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml @@ -96,7 +96,6 @@ properties: required: - compatible - reg - - interrupts - regulators additionalProperties: false diff --git a/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml b/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml new file mode 100644 index 000000000000..3aaa9653419a --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/qcom,qca6390-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCA6390 PMU Regulators + +maintainers: + - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> + +description: + The QCA6390 package contains discrete modules for WLAN and Bluetooth. They + are powered by the Power Management Unit (PMU) that takes inputs from the + host and provides LDO outputs. This document describes this module. + +properties: + compatible: + enum: + - qcom,qca6390-pmu + - qcom,wcn7850-pmu + + vdd-supply: + description: VDD supply regulator handle + + vddaon-supply: + description: VDD_AON supply regulator handle + + vdddig-supply: + description: VDD_DIG supply regulator handle + + vddpmu-supply: + description: VDD_PMU supply regulator handle + + vddio1p2-supply: + description: VDD_IO_1P2 supply regulator handle + + vddrfa0p95-supply: + description: VDD_RFA_0P95 supply regulator handle + + vddrfa1p2-supply: + description: VDD_RFA_1P2 supply regulator handle + + vddrfa1p3-supply: + description: VDD_RFA_1P3 supply regulator handle + + vddrfa1p8-supply: + description: VDD_RFA_1P8 supply regulator handle + + vddrfa1p9-supply: + description: VDD_RFA_1P9 supply regulator handle + + vddpcie1p3-supply: + description: VDD_PCIE_1P3 supply regulator handle + + vddpcie1p9-supply: + description: VDD_PCIE_1P9 supply regulator handle + + vddio-supply: + description: VDD_IO supply regulator handle + + wlan-enable-gpios: + maxItems: 1 + description: GPIO line enabling the ATH11K WLAN module supplied by the PMU + + bt-enable-gpios: + maxItems: 1 + description: GPIO line enabling the ATH11K Bluetooth module supplied by the PMU + + clocks: + maxItems: 1 + description: Reference clock handle + + regulators: + type: object + description: + LDO outputs of the PMU + + patternProperties: + "^ldo[0-9]$": + $ref: regulator.yaml# + type: object + unevaluatedProperties: false + + additionalProperties: false + +required: + - compatible + - regulators + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,qca6390-pmu + then: + required: + - vddaon-supply + - vddpmu-supply + - vddrfa0p95-supply + - vddrfa1p3-supply + - vddrfa1p9-supply + - vddpcie1p3-supply + - vddpcie1p9-supply + - vddio-supply + - if: + properties: + compatible: + contains: + const: qcom,wcn7850-pmu + then: + required: + - vdd-supply + - vddio-supply + - vddaon-supply + - vdddig-supply + - vddrfa1p2-supply + - vddrfa1p8-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + pmu { + compatible = "qcom,qca6390-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_state>, <&wlan_en_state>; + + vddaon-supply = <&vreg_s6a_0p95>; + vddpmu-supply = <&vreg_s2f_0p95>; + vddrfa0p95-supply = <&vreg_s2f_0p95>; + vddrfa1p3-supply = <&vreg_s8c_1p3>; + vddrfa1p9-supply = <&vreg_s5a_1p9>; + vddpcie1p3-supply = <&vreg_s8c_1p3>; + vddpcie1p9-supply = <&vreg_s5a_1p9>; + vddio-supply = <&vreg_s4a_1p8>; + + wlan-enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml b/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml index 609c06615bdc..87accc6f13b8 100644 --- a/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml +++ b/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml @@ -75,6 +75,12 @@ properties: description: regulator description for ldo[1-2]. + properties: + richtek,fixed-microvolt: + description: | + This property can be used to set a fixed operating voltage that lies outside + the range of the regulator's adjustable mode. + required: - compatible - reg @@ -177,6 +183,8 @@ examples: }; }; ldo1 { + /* Fixed LDO VOUT */ + richtek,fixed-microvolt = <1200000>; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -185,7 +193,8 @@ examples: }; }; ldo2 { - regulator-min-microvolt = <3300000>; + /* Adjustable LDO VOUT */ + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-state-mem { diff --git a/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.txt b/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.txt deleted file mode 100644 index 63dc07877cd6..000000000000 --- a/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.txt +++ /dev/null @@ -1,43 +0,0 @@ -Spreadtrum SC2731 Voltage regulators - -The SC2731 integrates low-voltage and low quiescent current DCDC/LDO. -14 LDO and 3 DCDCs are designed for external use. All DCDCs/LDOs have -their own bypass (power-down) control signals. External tantalum or MLCC -ceramic capacitors are recommended to use with these LDOs. - -Required properties: - - compatible: should be "sprd,sc27xx-regulator". - -List of regulators provided by this controller. It is named according to -its regulator type, BUCK_<name> and LDO_<name>. The definition for each -of these nodes is defined using the standard binding for regulators at -Documentation/devicetree/bindings/regulator/regulator.txt. - -The valid names for regulators are: -BUCK: - BUCK_CPU0, BUCK_CPU1, BUCK_RF -LDO: - LDO_CAMA0, LDO_CAMA1, LDO_CAMMOT, LDO_VLDO, LDO_EMMCCORE, LDO_SDCORE, - LDO_SDIO, LDO_WIFIPA, LDO_USB33, LDO_CAMD0, LDO_CAMD1, LDO_CON, - LDO_CAMIO, LDO_SRAM - -Example: - regulators { - compatible = "sprd,sc27xx-regulator"; - - vddarm0: BUCK_CPU0 { - regulator-name = "vddarm0"; - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1996875>; - regulator-ramp-delay = <25000>; - regulator-always-on; - }; - - vddcama0: LDO_CAMA0 { - regulator-name = "vddcama0"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.yaml b/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.yaml new file mode 100644 index 000000000000..ffb2924dde36 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/sprd,sc2731-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SC2731 Power Management IC regulators + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +description: | + The SC2731 integrates low-voltage and low quiescent current DCDC/LDO. + 14 LDO and 3 DCDCs are designed for external use. All DCDCs/LDOs have + their own bypass (power-down) control signals. It is recommended to use + external tantalum or MLCC ceramic capacitors with these LDOs. + Valid names for the regulators are: + BUCK: + BUCK_CPU0, BUCK_CPU1, BUCK_RF + LDO: + LDO_CAMA0, LDO_CAMA1, LDO_CAMD0, LDO_CAMD1, LDO_CAMIO, LDO_CAMMOT, + LDO_CON, LDO_EMMCCORE, LDO_SDCORE, LDO_SDIO, LDO_SRAM, LDO_USB33, + LDO_VLDO, LDO_WIFIPA + +properties: + compatible: + const: sprd,sc2731-regulator + +patternProperties: + "^BUCK_(CPU[0-1]|RF)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^LDO_(CAM(A0|A1|D0|D1|IO|MOT)|CON|EMMCCORE|SD(CORE|IO)|SRAM|USB33|VLDO|WIFIPA)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + regulators { + compatible = "sprd,sc2731-regulator"; + + BUCK_CPU0 { + regulator-name = "vddarm0"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1996875>; + regulator-ramp-delay = <25000>; + regulator-always-on; + }; + + LDO_CAMA0 { + regulator-name = "vddcama0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + regulator-enable-ramp-delay = <100>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml b/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml index c9586d277f41..3cb2dad18781 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml @@ -11,7 +11,12 @@ maintainers: properties: compatible: - const: st,stm32mp1,pwr-reg + oneOf: + - items: + - const: st,stm32mp1,pwr-reg + - items: + - const: st,stm32mp13-pwr-reg + - const: st,stm32mp1,pwr-reg reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/regulator/ti,tps65132.yaml b/Documentation/devicetree/bindings/regulator/ti,tps65132.yaml index 6a6d1a3d6fa7..873d92738eb0 100644 --- a/Documentation/devicetree/bindings/regulator/ti,tps65132.yaml +++ b/Documentation/devicetree/bindings/regulator/ti,tps65132.yaml @@ -23,6 +23,8 @@ properties: reg: maxItems: 1 + vin-supply: true + patternProperties: "^out[pn]$": type: object @@ -65,6 +67,7 @@ examples: regulator@3e { compatible = "ti,tps65132"; reg = <0x3e>; + vin-supply = <&supply>; outp { regulator-name = "outp"; diff --git a/Documentation/devicetree/bindings/regulator/twl-regulator.txt b/Documentation/devicetree/bindings/regulator/twl-regulator.txt deleted file mode 100644 index 549f80436deb..000000000000 --- a/Documentation/devicetree/bindings/regulator/twl-regulator.txt +++ /dev/null @@ -1,80 +0,0 @@ -TWL family of regulators - -Required properties: -For twl6030 regulators/LDOs -- compatible: - - "ti,twl6030-vaux1" for VAUX1 LDO - - "ti,twl6030-vaux2" for VAUX2 LDO - - "ti,twl6030-vaux3" for VAUX3 LDO - - "ti,twl6030-vmmc" for VMMC LDO - - "ti,twl6030-vpp" for VPP LDO - - "ti,twl6030-vusim" for VUSIM LDO - - "ti,twl6030-vana" for VANA LDO - - "ti,twl6030-vcxio" for VCXIO LDO - - "ti,twl6030-vdac" for VDAC LDO - - "ti,twl6030-vusb" for VUSB LDO - - "ti,twl6030-v1v8" for V1V8 LDO - - "ti,twl6030-v2v1" for V2V1 LDO - - "ti,twl6030-vdd1" for VDD1 SMPS - - "ti,twl6030-vdd2" for VDD2 SMPS - - "ti,twl6030-vdd3" for VDD3 SMPS -For twl6032 regulators/LDOs -- compatible: - - "ti,twl6032-ldo1" for LDO1 LDO - - "ti,twl6032-ldo2" for LDO2 LDO - - "ti,twl6032-ldo3" for LDO3 LDO - - "ti,twl6032-ldo4" for LDO4 LDO - - "ti,twl6032-ldo5" for LDO5 LDO - - "ti,twl6032-ldo6" for LDO6 LDO - - "ti,twl6032-ldo7" for LDO7 LDO - - "ti,twl6032-ldoln" for LDOLN LDO - - "ti,twl6032-ldousb" for LDOUSB LDO - - "ti,twl6032-smps3" for SMPS3 SMPS - - "ti,twl6032-smps4" for SMPS4 SMPS - - "ti,twl6032-vio" for VIO SMPS -For twl4030 regulators/LDOs -- compatible: - - "ti,twl4030-vaux1" for VAUX1 LDO - - "ti,twl4030-vaux2" for VAUX2 LDO - - "ti,twl5030-vaux2" for VAUX2 LDO - - "ti,twl4030-vaux3" for VAUX3 LDO - - "ti,twl4030-vaux4" for VAUX4 LDO - - "ti,twl4030-vmmc1" for VMMC1 LDO - - "ti,twl4030-vmmc2" for VMMC2 LDO - - "ti,twl4030-vpll1" for VPLL1 LDO - - "ti,twl4030-vpll2" for VPLL2 LDO - - "ti,twl4030-vsim" for VSIM LDO - - "ti,twl4030-vdac" for VDAC LDO - - "ti,twl4030-vintana2" for VINTANA2 LDO - - "ti,twl4030-vio" for VIO LDO - - "ti,twl4030-vdd1" for VDD1 SMPS - - "ti,twl4030-vdd2" for VDD2 SMPS - - "ti,twl4030-vintana1" for VINTANA1 LDO - - "ti,twl4030-vintdig" for VINTDIG LDO - - "ti,twl4030-vusb1v5" for VUSB1V5 LDO - - "ti,twl4030-vusb1v8" for VUSB1V8 LDO - - "ti,twl4030-vusb3v1" for VUSB3V1 LDO - -Optional properties: -- Any optional property defined in bindings/regulator/regulator.txt -For twl4030 regulators/LDOs: - - regulator-initial-mode: - - 0x08 - Sleep mode, the nominal output voltage is maintained with low power - consumption with low load current capability. - - 0x0e - Active mode, the regulator can deliver its nominal output voltage - with full-load current capability. - -Example: - - xyz: regulator@0 { - compatible = "ti,twl6030-vaux1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; - -For twl6030 regulators/LDOs: - - - ti,retain-on-reset: Does not turn off the supplies during warm - reset. Could be needed for VMMC, as TWL6030 - reset sequence for this signal does not comply - with the SD specification. diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml index 03c18611e42d..b0b20af15313 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -42,6 +42,12 @@ properties: 0 = Port 1 Phy reset 1 = Port 2 Phy reset + regulator-vbus: + type: object + description: USB VBUS regulator + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + required: - compatible - reg @@ -49,6 +55,7 @@ required: - resets - power-domains - '#reset-cells' + - regulator-vbus additionalProperties: false @@ -64,4 +71,7 @@ examples: resets = <&cpg R9A07G044_USB_PRESETN>; power-domains = <&cpg>; #reset-cells = <1>; + regulator-vbus { + regulator-name = "vbus"; + }; }; diff --git a/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml b/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml index e10eb98eddad..1db08ce9ae27 100644 --- a/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml +++ b/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml @@ -37,7 +37,7 @@ properties: The second cell should contain the reset mask corresponding to the device used by system controller. - Please see http://processors.wiki.ti.com/index.php/TISCI for + Please see https://software-dl.ti.com/tisci/esd/latest/index.html for protocol documentation for the values to be used for different devices. diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..d067f2a468ee 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -47,6 +47,7 @@ properties: - sifive,u74 - sifive,u74-mc - thead,c906 + - thead,c908 - thead,c910 - thead,c920 - const: riscv diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 4a29c890619a..78ce76ae1b6d 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -29,6 +29,7 @@ properties: - enum: - aldec,tysom-m-mpfs250t-rev2 - aries,m100pfsevp + - beagle,beaglev-fire - microchip,mpfs-sev-kit - sundance,polarberry - const: microchip,mpfs diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index b672f8521949..4d5c857b3cac 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - milkv,mars + - pine64,star64 - starfive,visionfive-2-v1.2a - starfive,visionfive-2-v1.3b - const: starfive,jh7110 diff --git a/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt b/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt deleted file mode 100644 index d10cc06c0c37..000000000000 --- a/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt +++ /dev/null @@ -1,64 +0,0 @@ -Device tree bindings for Marvell PXA SSP ports - -Required properties: - - - compatible: Must be one of - mrvl,pxa25x-ssp - mvrl,pxa25x-nssp - mrvl,pxa27x-ssp - mrvl,pxa3xx-ssp - mvrl,pxa168-ssp - mrvl,pxa910-ssp - mrvl,ce4100-ssp - - - reg: The memory base - - dmas: Two dma phandles, one for rx, one for tx - - dma-names: Must be "rx", "tx" - - -Example for PXA3xx: - - ssp0: ssp@41000000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41000000 0x40>; - ssp-id = <1>; - interrupts = <24>; - clock-names = "pxa27x-ssp.0"; - dmas = <&dma 13 - &dma 14>; - dma-names = "rx", "tx"; - }; - - ssp1: ssp@41700000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41700000 0x40>; - ssp-id = <2>; - interrupts = <16>; - clock-names = "pxa27x-ssp.1"; - dmas = <&dma 15 - &dma 16>; - dma-names = "rx", "tx"; - }; - - ssp2: ssp@41900000 { - compatibl3 = "mrvl,pxa3xx-ssp"; - reg = <0x41900000 0x40>; - ssp-id = <3>; - interrupts = <0>; - clock-names = "pxa27x-ssp.2"; - dmas = <&dma 66 - &dma 67>; - dma-names = "rx", "tx"; - }; - - ssp3: ssp@41a00000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41a00000 0x40>; - ssp-id = <4>; - interrupts = <13>; - clock-names = "pxa27x-ssp.3"; - dmas = <&dma 2 - &dma 3>; - dma-names = "rx", "tx"; - }; - diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml index ce1a6505eb51..3fb0534ea597 100644 --- a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml @@ -8,7 +8,6 @@ title: Freescale Layerscape Device Configuration Unit maintainers: - Shawn Guo <shawnguo@kernel.org> - - Li Yang <leoyang.li@nxp.com> description: | DCFG is the device configuration unit, that provides general purpose diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml index a6a511b00a12..2a456c8af992 100644 --- a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml @@ -8,7 +8,6 @@ title: Freescale Layerscape Supplemental Configuration Unit maintainers: - Shawn Guo <shawnguo@kernel.org> - - Li Yang <leoyang.li@nxp.com> description: | SCFG is the supplemental configuration unit, that provides SoC specific diff --git a/Documentation/devicetree/bindings/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml b/Documentation/devicetree/bindings/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml new file mode 100644 index 000000000000..5c77c4925d19 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Kirin 960 USB OTG Battery Charging Syscon + +maintainers: + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> + +properties: + compatible: + items: + - const: hisilicon,hi3660-usb3-otg-bc + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + usb-phy: + $ref: /schemas/phy/hisilicon,hi3660-usb3.yaml + description: USB Phy node + +required: + - compatible + - reg + - usb-phy + +additionalProperties: false + +examples: + - | + syscon@ff200000 { + compatible = "hisilicon,hi3660-usb3-otg-bc", "syscon", "simple-mfd"; + reg = <0xff200000 0x1000>; + + usb-phy { + compatible = "hisilicon,hi3660-usb-phy"; + #phy-cells = <0>; + hisilicon,pericrg-syscon = <&crg_ctrl>; + hisilicon,pctrl-syscon = <&pctrl>; + hisilicon,eye-diagram-param = <0x22466e4>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index ba2014a8725c..a10326a9683d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt8186-disp-mutex - mediatek,mt8186-mdp3-mutex - mediatek,mt8188-disp-mutex + - mediatek,mt8188-vpp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex - mediatek,mt8195-vpp-mutex diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index b4478f417edc..7afdb60edb22 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -31,6 +31,7 @@ properties: - qcom,sc7280-aoss-qmp - qcom,sc8180x-aoss-qmp - qcom,sc8280xp-aoss-qmp + - qcom,sdx75-aoss-qmp - qcom,sdm845-aoss-qmp - qcom,sm6350-aoss-qmp - qcom,sm8150-aoss-qmp diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml index 58500529b90f..141d666dc3f7 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml @@ -41,6 +41,7 @@ properties: description: Three entries specifying the outgoing ipc bit used for signaling the remote end of the smp2p edge. + deprecated: true qcom,local-pid: $ref: /schemas/types.yaml#/definitions/uint32 @@ -128,7 +129,7 @@ examples: compatible = "qcom,smp2p"; qcom,smem = <431>, <451>; interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 18>; + mboxes = <&apcs 18>; qcom,local-pid = <0>; qcom,remote-pid = <4>; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml index db67cf043256..4900215f26af 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml @@ -33,6 +33,14 @@ properties: specifier of the column in the subscription matrix representing the local processor. + mboxes: + minItems: 1 + maxItems: 5 + description: + Reference to the mailbox representing the outgoing doorbell in APCS for + this client. Each entry represents the N:th remote processor by index + (0-indexed). + '#size-cells': const: 0 @@ -47,6 +55,7 @@ patternProperties: description: Three entries specifying the outgoing ipc bit used for signaling the N:th remote processor. + deprecated: true "@[0-9a-f]$": type: object @@ -98,15 +107,18 @@ required: - '#address-cells' - '#size-cells' -anyOf: - - required: - - qcom,ipc-1 - - required: - - qcom,ipc-2 - - required: - - qcom,ipc-3 +oneOf: - required: - - qcom,ipc-4 + - mboxes + - anyOf: + - required: + - qcom,ipc-1 + - required: + - qcom,ipc-2 + - required: + - qcom,ipc-3 + - required: + - qcom,ipc-4 additionalProperties: false @@ -122,7 +134,7 @@ examples: compatible = "qcom,smsm"; #address-cells = <1>; #size-cells = <0>; - qcom,ipc-3 = <&apcs 8 19>; + mboxes = <0>, <0>, <0>, <&apcs 19>; apps_smsm: apps@0 { reg = <0>; diff --git a/Documentation/devicetree/bindings/soc/sti/st,sti-syscon.yaml b/Documentation/devicetree/bindings/soc/sti/st,sti-syscon.yaml index 5f97d9ff17fb..fc933d70d138 100644 --- a/Documentation/devicetree/bindings/soc/sti/st,sti-syscon.yaml +++ b/Documentation/devicetree/bindings/soc/sti/st,sti-syscon.yaml @@ -30,6 +30,15 @@ properties: reg: maxItems: 1 + sti-sasg-codec: + description: STi internal audio codec + type: object + additionalProperties: true + + properties: + compatible: + const: st,stih407-sas-codec + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml index a750035d6234..b6da72032151 100644 --- a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml +++ b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml @@ -40,7 +40,7 @@ properties: TI_SCI_PD_SHARED - Allows the device to be shared by multiple hosts. Please refer to dt-bindings/soc/ti,sci_pm_domain.h for the definitions. - Please see http://processors.wiki.ti.com/index.php/TISCI for + Please see https://software-dl.ti.com/tisci/esd/latest/index.html for protocol documentation for the values to be used for different devices. additionalProperties: false diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml index e6289fbe6907..378e9cc5fac2 100644 --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml @@ -2,7 +2,7 @@ # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ %YAML 1.2 --- -$id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml# +$id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI J721e System Controller Registers R/W @@ -19,7 +19,7 @@ description: | and access the registers directly. maintainers: - - Kishon Vijay Abraham I <kishon@ti.com> + - Kishon Vijay Abraham I <kishon@kernel.org> - Roger Quadros <rogerq@kernel.org> properties: diff --git a/Documentation/devicetree/bindings/spi/amlogic,a1-spifc.yaml b/Documentation/devicetree/bindings/spi/amlogic,a1-spifc.yaml index ea47d30eef43..043879b434ac 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,a1-spifc.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,a1-spifc.yaml @@ -23,6 +23,9 @@ properties: clocks: maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml index 32e7c14033c2..d29772994cf5 100644 --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml @@ -18,10 +18,10 @@ properties: oneOf: - const: atmel,at91rm9200-spi - items: - - const: microchip,sam9x60-spi - - const: atmel,at91rm9200-spi - - items: - - const: microchip,sam9x7-spi + - enum: + - microchip,sam9x60-spi + - microchip,sam9x7-spi + - microchip,sama7d65-spi - const: atmel,at91rm9200-spi reg: diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt deleted file mode 100644 index 3d55dd64b1be..000000000000 --- a/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt +++ /dev/null @@ -1,23 +0,0 @@ -Broadcom BCM2835 SPI0 controller - -The BCM2835 contains two forms of SPI master controller, one known simply as -SPI0, and the other known as the "Universal SPI Master"; part of the -auxiliary block. This binding applies to the SPI0 controller. - -Required properties: -- compatible: Should be one of "brcm,bcm2835-spi" for BCM2835/2836/2837 or - "brcm,bcm2711-spi" for BCM2711 or "brcm,bcm7211-spi" for BCM7211. -- reg: Should contain register location and length. -- interrupts: Should contain interrupt. -- clocks: The clock feeding the SPI controller. - -Example: - -spi@20204000 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204000 0x1000>; - interrupts = <2 22>; - clocks = <&clk_spi>; - #address-cells = <1>; - #size-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.yaml b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.yaml new file mode 100644 index 000000000000..94da68792194 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/brcm,bcm2835-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 SPI0 controller + +maintainers: + - Florian Fainelli <florian.fainelli@broadcom.com> + - Kanak Shilledar <kanakshilledar111@protonmail.com> + - Stefan Wahren <wahrenst@gmx.net> + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + enum: + - brcm,bcm2835-spi + - brcm,bcm2711-spi + - brcm,bcm7211-spi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + spi@20204000 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204000 0x1000>; + interrupts = <2 22>; + clocks = <&clk_spi>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/spi/fsl,dspi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/fsl,dspi-peripheral-props.yaml new file mode 100644 index 000000000000..9b62b75e17a7 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/fsl,dspi-peripheral-props.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/fsl,dspi-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral-specific properties for Freescale DSPI controller + +maintainers: + - Vladimir Oltean <olteanv@gmail.com> + +description: + See spi-peripheral-props.yaml for more info. + +properties: + fsl,spi-cs-sck-delay: + deprecated: true + description: + Delay in nanoseconds between activating chip select and the start of + clock signal, at the start of a transfer. + $ref: /schemas/types.yaml#/definitions/uint32 + + fsl,spi-sck-cs-delay: + deprecated: true + description: + Delay in nanoseconds between stopping the clock signal and + deactivating chip select, at the end of a transfer. + $ref: /schemas/types.yaml#/definitions/uint32 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/spi/fsl,dspi.yaml b/Documentation/devicetree/bindings/spi/fsl,dspi.yaml new file mode 100644 index 000000000000..7ca8fceda717 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/fsl,dspi.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/fsl,dspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Freescale DSPI controller + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + oneOf: + - enum: + - fsl,vf610-dspi + - fsl,ls1021a-v1.0-dspi + - fsl,ls1012a-dspi + - fsl,ls1028a-dspi + - fsl,ls1043a-dspi + - fsl,ls1046a-dspi + - fsl,ls1088a-dspi + - fsl,ls2080a-dspi + - fsl,ls2085a-dspi + - fsl,lx2160a-dspi + - items: + - enum: + - fsl,ls1012a-dspi + - fsl,ls1028a-dspi + - fsl,ls1043a-dspi + - fsl,ls1046a-dspi + - fsl,ls1088a-dspi + - const: fsl,ls1021a-v1.0-dspi + - items: + - const: fsl,ls2080a-dspi + - const: fsl,ls2085a-dspi + - items: + - const: fsl,lx2160a-dspi + - const: fsl,ls2085a-dspi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: dspi + + dmas: + items: + - description: DMA controller phandle and request line for TX + - description: DMA controller phandle and request line for RX + + dma-names: + items: + - const: tx + - const: rx + + spi-num-chipselects: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The number of the chip native chipselect signals. + cs-gpios don't count against this number. + + big-endian: true + + bus-num: + $ref: /schemas/types.yaml#/definitions/uint32 + description: SoC-specific identifier for the SPI controller. + +required: + - compatible + - reg + - clocks + - clock-names + - spi-num-chipselects + +allOf: + - $ref: spi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/vf610-clock.h> + + spi@4002c000 { + compatible = "fsl,vf610-dspi"; + reg = <0x4002c000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_DSPI0>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi0_1>; + big-endian; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + spi-cs-setup-delay-ns = <100>; + spi-cs-hold-delay-ns = <50>; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/ibm,spi-fsi.yaml b/Documentation/devicetree/bindings/spi/ibm,spi-fsi.yaml new file mode 100644 index 000000000000..d7fec4c3a801 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/ibm,spi-fsi.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/ibm,spi-fsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached SPI Controller + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + A SPI controller found on IBM Power processors, accessed over FSI from a + service processor. This node will always be a child node of an ibm,fsi2spi + node. + +properties: + compatible: + enum: + - ibm,spi-fsi + + reg: + maxItems: 1 + +required: + - compatible + - reg + +allOf: + - $ref: spi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + fsi { + #address-cells = <1>; + #size-cells = <0>; + + spi@0 { + compatible = "ibm,spi-fsi"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + size = <0x80000>; + address-width = <24>; + pagesize = <256>; + spi-max-frequency = <1000000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml b/Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml index 5f4f6b5615d0..0a1bada8f800 100644 --- a/Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml +++ b/Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml @@ -10,12 +10,17 @@ title: PXA2xx SSP SPI Controller maintainers: - Lubomir Rintel <lkundrak@v3.sk> -allOf: - - $ref: spi-controller.yaml# - properties: compatible: - const: marvell,mmp2-ssp + enum: + - marvell,mmp2-ssp + - mrvl,ce4100-ssp + - mvrl,pxa168-ssp + - mrvl,pxa25x-ssp + - mvrl,pxa25x-nssp + - mrvl,pxa27x-ssp + - mrvl,pxa3xx-ssp + - mrvl,pxa910-ssp interrupts: maxItems: 1 @@ -26,6 +31,16 @@ properties: clocks: maxItems: 1 + dmas: + items: + - description: Receive DMA + - description: Transmit DMA + + dma-names: + items: + - const: rx + - const: tx + ready-gpios: description: | GPIO used to signal a SPI master that the FIFO is filled and we're @@ -41,6 +56,18 @@ required: dependencies: ready-gpios: [ spi-slave ] +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + const: marvell,mmp2-ssp + then: + properties: + dmas: false + dma-names: false + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml index 74a817cc7d94..ffa8d1b48f8b 100644 --- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml @@ -13,9 +13,6 @@ description: maintainers: - Conor Dooley <conor.dooley@microchip.com> -allOf: - - $ref: spi-controller.yaml# - properties: compatible: oneOf: @@ -43,6 +40,32 @@ required: - interrupts - clocks +allOf: + - $ref: spi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: microchip,mpfs-spi + then: + properties: + num-cs: + default: 1 + + - if: + properties: + compatible: + contains: + const: microchip,mpfs-spi + not: + required: + - cs-gpios + then: + properties: + num-cs: + maximum: 1 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index fde3776a558b..bccd00a1ddd0 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -88,6 +88,10 @@ properties: - renesas,r9a06g032-spi # RZ/N1D - renesas,r9a06g033-spi # RZ/N1S - const: renesas,rzn1-spi # RZ/N1 + - description: T-HEAD TH1520 SoC SPI Controller + items: + - const: thead,th1520-spi + - const: snps,dw-apb-ssi reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml index d4b61b0e8301..8de96abe9da1 100644 --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml @@ -55,6 +55,13 @@ properties: label: description: Descriptive name of the SPI controller. + resets: + maxItems: 1 + + reset-names: + items: + - const: spi + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt deleted file mode 100644 index 30a79da9c039..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ /dev/null @@ -1,65 +0,0 @@ -ARM Freescale DSPI controller - -Required properties: -- compatible : must be one of: - "fsl,vf610-dspi", - "fsl,ls1021a-v1.0-dspi", - "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), - "fsl,ls1028a-dspi", - "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), - "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), - "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), - "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"), - "fsl,ls2085a-dspi", - "fsl,lx2160a-dspi", -- reg : Offset and length of the register set for the device -- interrupts : Should contain SPI controller interrupt -- clocks: from common clock binding: handle to dspi clock. -- clock-names: from common clock binding: Shall be "dspi". -- pinctrl-0: pin control group to be used for this controller. -- pinctrl-names: must contain a "default" entry. -- spi-num-chipselects : the number of the chipselect signals. - -Optional property: -- big-endian: If present the dspi device's registers are implemented - in big endian mode. -- bus-num : the slave chip chipselect signal number. - -Optional SPI slave node properties: -- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip - select and the start of clock signal, at the start of a transfer. -- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock - signal and deactivating chip select, at the end of a transfer. - -Example: - -dspi0@4002c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x4002c000 0x1000>; - interrupts = <0 67 0x04>; - clocks = <&clks VF610_CLK_DSPI0>; - clock-names = "dspi"; - spi-num-chipselects = <5>; - bus-num = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0_1>; - big-endian; - - sflash: at26df081a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at26df081a"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - linux,modalias = "m25p80"; - modal = "at26df081a"; - fsl,spi-cs-sck-delay = <100>; - fsl,spi-sck-cs-delay = <50>; - }; -}; - - diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 15938f81fdce..0bb443b8decd 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -122,6 +122,7 @@ properties: allOf: - $ref: arm,pl022-peripheral-props.yaml# - $ref: cdns,qspi-nor-peripheral-props.yaml# + - $ref: fsl,dspi-peripheral-props.yaml# - $ref: samsung,spi-peripheral-props.yaml# - $ref: nvidia,tegra210-quad-peripheral-props.yaml# diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index cf07b8f787a6..d9322704f358 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -56,6 +56,9 @@ properties: ranges: true patternProperties: + "^regulators@[0-9a-f]+$": + $ref: /schemas/regulator/allwinner,sun20i-d1-system-ldos.yaml# + "^sram@[a-f0-9]+": $ref: /schemas/sram/sram.yaml# unevaluatedProperties: false @@ -130,3 +133,28 @@ examples: }; }; }; + + - | + syscon@3000000 { + compatible = "allwinner,sun20i-d1-system-control"; + reg = <0x3000000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + regulators@3000150 { + compatible = "allwinner,sun20i-d1-system-ldos"; + reg = <0x3000150 0x4>; + + reg_ldoa: ldoa { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_ldob: ldob { + regulator-name = "vcc-dram"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index 8025a852bc9c..faef3d6e0a94 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -22,6 +22,7 @@ properties: - qcom,msm8974-imem - qcom,qcs404-imem - qcom,qdu1000-imem + - qcom,sa8775p-imem - qcom,sc7180-imem - qcom,sc7280-imem - qcom,sdm630-imem diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml index 6b3aea6d73b0..dad8de900495 100644 --- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -10,6 +10,8 @@ maintainers: - Vasily Khoruzhick <anarsoul@gmail.com> - Yangtao Li <tiny.windzz@gmail.com> +$ref: thermal-sensor.yaml# + properties: compatible: enum: @@ -55,7 +57,6 @@ properties: maxItems: 1 description: phandle to device controlling temperate offset SYS_CFG register - # See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details "#thermal-sensor-cells": enum: - 0 @@ -135,9 +136,8 @@ required: - compatible - reg - interrupts - - '#thermal-sensor-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml index 01fccdfc4178..725303e1a364 100644 --- a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml @@ -11,6 +11,8 @@ maintainers: description: Binding for Amlogic Thermal +$ref: thermal-sensor.yaml# + properties: compatible: oneOf: @@ -44,17 +46,17 @@ required: - clocks - amlogic,ao-secure -additionalProperties: false +unevaluatedProperties: false examples: - | - cpu_temp: temperature-sensor@ff634800 { - compatible = "amlogic,g12a-cpu-thermal", - "amlogic,g12a-thermal"; - reg = <0xff634800 0x50>; - interrupts = <0x0 0x24 0x0>; - clocks = <&clk 164>; - #thermal-sensor-cells = <0>; - amlogic,ao-secure = <&sec_AO>; - }; + temperature-sensor@ff634800 { + compatible = "amlogic,g12a-cpu-thermal", + "amlogic,g12a-thermal"; + reg = <0xff634800 0x50>; + interrupts = <0x0 0x24 0x0>; + clocks = <&clk 164>; + #thermal-sensor-cells = <0>; + amlogic,ao-secure = <&sec_AO>; + }; ... diff --git a/Documentation/devicetree/bindings/thermal/brcm,avs-ro-thermal.yaml b/Documentation/devicetree/bindings/thermal/brcm,avs-ro-thermal.yaml index 89a2c32c0ab2..29a9844e8b48 100644 --- a/Documentation/devicetree/bindings/thermal/brcm,avs-ro-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/brcm,avs-ro-thermal.yaml @@ -19,30 +19,30 @@ description: |+ Refer to the bindings described in Documentation/devicetree/bindings/mfd/syscon.yaml +$ref: thermal-sensor.yaml# + properties: compatible: const: brcm,bcm2711-thermal - # See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details "#thermal-sensor-cells": const: 0 required: - compatible - - '#thermal-sensor-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | - avs-monitor@7d5d2000 { - compatible = "brcm,bcm2711-avs-monitor", - "syscon", "simple-mfd"; - reg = <0x7d5d2000 0xf00>; - - thermal: thermal { - compatible = "brcm,bcm2711-thermal"; - #thermal-sensor-cells = <0>; - }; + avs-monitor@7d5d2000 { + compatible = "brcm,bcm2711-avs-monitor", + "syscon", "simple-mfd"; + reg = <0x7d5d2000 0xf00>; + + thermal: thermal { + compatible = "brcm,bcm2711-thermal"; + #thermal-sensor-cells = <0>; }; + }; ... diff --git a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml index 267a0f423504..081486b44382 100644 --- a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml +++ b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml @@ -42,15 +42,14 @@ additionalProperties: false required: - compatible - reg - - "#thermal-sensor-cells" examples: - | - thermal@f04d1500 { - compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon"; - reg = <0xf04d1500 0x28>; - interrupts = <0x6>; - interrupt-names = "tmon"; - interrupt-parent = <&avs_host_l2_intc>; - #thermal-sensor-cells = <0>; - }; + thermal@f04d1500 { + compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon"; + reg = <0xf04d1500 0x28>; + interrupts = <0x6>; + interrupt-names = "tmon"; + interrupt-parent = <&avs_host_l2_intc>; + #thermal-sensor-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.yaml b/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.yaml index 2b6026d9fbcf..ddf0f20e5285 100644 --- a/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.yaml @@ -34,7 +34,6 @@ required: - compatible - reg - clocks - - '#thermal-sensor-cells' examples: - | diff --git a/Documentation/devicetree/bindings/thermal/fsl,scu-thermal.yaml b/Documentation/devicetree/bindings/thermal/fsl,scu-thermal.yaml index e02d04d4f71e..ceef318668bf 100644 --- a/Documentation/devicetree/bindings/thermal/fsl,scu-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/fsl,scu-thermal.yaml @@ -28,7 +28,6 @@ properties: required: - compatible - - '#thermal-sensor-cells' additionalProperties: false diff --git a/Documentation/devicetree/bindings/thermal/generic-adc-thermal.yaml b/Documentation/devicetree/bindings/thermal/generic-adc-thermal.yaml index f1fc3b0d8608..12e6418dc24d 100644 --- a/Documentation/devicetree/bindings/thermal/generic-adc-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/generic-adc-thermal.yaml @@ -15,6 +15,8 @@ description: sensor resistor. The voltage read across the sensor is mapped to temperature using voltage-temperature lookup table. +$ref: thermal-sensor.yaml# + properties: compatible: const: generic-adc-thermal @@ -44,11 +46,10 @@ properties: required: - compatible - - '#thermal-sensor-cells' - io-channels - io-channel-names -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/thermal/hisilicon,tsensor.yaml b/Documentation/devicetree/bindings/thermal/hisilicon,tsensor.yaml new file mode 100644 index 000000000000..11aca2b749d7 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/hisilicon,tsensor.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/hisilicon,tsensor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Temperature Sensor on HiSilicon SoCs + +maintainers: + - Abdulrasaq Lawani <abdulrasaqolawani@gmail.com> + +allOf: + - $ref: thermal-sensor.yaml + +properties: + compatible: + enum: + - hisilicon,tsensor + - hisilicon,hi3660-tsensor + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: thermal_clk + + interrupts: + maxItems: 1 + + '#thermal-sensor-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#thermal-sensor-cells' + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/hi6220-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + temperature-sensor@f7030700 { + compatible = "hisilicon,tsensor"; + reg = <0xf7030700 0x1000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_ctrl HI6220_TSENSOR_CLK>; + clock-names = "thermal_clk"; + #thermal-sensor-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt b/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt deleted file mode 100644 index 4b19d80e6558..000000000000 --- a/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Temperature Sensor on hisilicon SoCs - -** Required properties : - -- compatible: "hisilicon,tsensor". -- reg: physical base address of thermal sensor and length of memory mapped - region. -- interrupt: The interrupt number to the cpu. Defines the interrupt used - by /SOCTHERM/tsensor. -- clock-names: Input clock name, should be 'thermal_clk'. -- clocks: phandles for clock specified in "clock-names" property. -- #thermal-sensor-cells: Should be 1. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description. - -Example : - -for Hi6220: - tsensor: tsensor@0,f7030700 { - compatible = "hisilicon,tsensor"; - reg = <0x0 0xf7030700 0x0 0x1000>; - interrupts = <0 7 0x4>; - clocks = <&sys_ctrl HI6220_TSENSOR_CLK>; - clock-names = "thermal_clk"; - #thermal-sensor-cells = <1>; - } - -for Hi3660: - tsensor: tsensor@fff30000 { - compatible = "hisilicon,hi3660-tsensor"; - reg = <0x0 0xfff30000 0x0 0x1000>; - interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - #thermal-sensor-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml index d2c1e4573c32..e7ddaa6c966e 100644 --- a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml @@ -16,6 +16,8 @@ description: | for i.MX8MM which has ONLY 1 sensor, v2 is for i.MX8MP which has 2 sensors. +$ref: thermal-sensor.yaml# + properties: compatible: oneOf: @@ -51,9 +53,8 @@ required: - compatible - reg - clocks - - '#thermal-sensor-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/thermal/loongson,ls2k-thermal.yaml b/Documentation/devicetree/bindings/thermal/loongson,ls2k-thermal.yaml index ca81c8afba79..79e691b08341 100644 --- a/Documentation/devicetree/bindings/thermal/loongson,ls2k-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/loongson,ls2k-thermal.yaml @@ -38,7 +38,6 @@ required: - compatible - reg - interrupts - - '#thermal-sensor-cells' if: properties: diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml index 331cf4e662e3..0259cd3ce9c5 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -99,7 +99,6 @@ required: - resets - nvmem-cells - nvmem-cell-names - - "#thermal-sensor-cells" additionalProperties: false diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml index b0237d236021..19bb1f324183 100644 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml @@ -197,7 +197,6 @@ required: - clock-names - resets - reset-names - - "#thermal-sensor-cells" allOf: - $ref: thermal-sensor.yaml diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml index c91fd07e4061..978b9e6ab8a3 100644 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml @@ -20,11 +20,7 @@ description: | node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP binding. - This node represents a thermal sensor. See - - Documentation/devicetree/bindings/thermal/thermal-sensor.yaml - - for details of the core thermal binding. +$ref: thermal-sensor.yaml# properties: compatible: @@ -33,10 +29,6 @@ properties: - nvidia,tegra194-bpmp-thermal '#thermal-sensor-cells': - $ref: /schemas/types.yaml#/definitions/uint32 - description: Number of cells needed in the phandle specifier to - identify a given sensor. Must be 1 and the single cell specifies - the sensor index. const: 1 -additionalProperties: false +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml index a35da257b070..63a29a1f7fe6 100644 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml @@ -27,6 +27,8 @@ description: | TSENSOR has two channels which monitor two different spots of the SoC. +$ref: thermal-sensor.yaml# + properties: compatible: const: nvidia,tegra30-tsensor @@ -46,19 +48,14 @@ properties: "#thermal-sensor-cells": const: 1 - assigned-clock-parents: true - assigned-clock-rates: true - assigned-clocks: true - required: - compatible - reg - clocks - resets - interrupts - - "#thermal-sensor-cells" -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/thermal/qcom,spmi-temp-alarm.yaml b/Documentation/devicetree/bindings/thermal/qcom,spmi-temp-alarm.yaml index 5f08b6e59b8a..30b22151aa82 100644 --- a/Documentation/devicetree/bindings/thermal/qcom,spmi-temp-alarm.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom,spmi-temp-alarm.yaml @@ -42,7 +42,6 @@ required: - compatible - reg - interrupts - - '#thermal-sensor-cells' additionalProperties: false diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml index 7541e27704ca..bfad8130a042 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml @@ -8,6 +8,8 @@ title: Qualcomm's SPMI PMIC ADC HC Thermal Monitoring maintainers: - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +$ref: thermal-sensor.yaml# + properties: compatible: const: qcom,spmi-adc-tm-hc @@ -20,9 +22,6 @@ properties: "#thermal-sensor-cells": const: 1 - description: - Number of cells required to uniquely identify the thermal sensors. Since - we have multiple sensors this is set to 1 "#address-cells": const: 1 @@ -106,9 +105,8 @@ required: - interrupts - "#address-cells" - "#size-cells" - - "#thermal-sensor-cells" -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml index d9d2657287cb..4470a5942fb2 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -8,6 +8,8 @@ title: Qualcomm's SPMI PMIC ADC Thermal Monitoring maintainers: - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +$ref: thermal-sensor.yaml# + properties: compatible: enum: @@ -23,9 +25,6 @@ properties: "#thermal-sensor-cells": const: 1 - description: - Number of cells required to uniquely identify the thermal sensors. Since - we have multiple sensors this is set to 1 "#address-cells": const: 1 @@ -159,9 +158,8 @@ required: - interrupts - "#address-cells" - "#size-cells" - - "#thermal-sensor-cells" -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 99d9c526c0b6..72048c5a0412 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -67,6 +67,7 @@ properties: - qcom,sm8450-tsens - qcom,sm8550-tsens - qcom,sm8650-tsens + - qcom,x1e80100-tsens - const: qcom,tsens-v2 - description: v2 of TSENS with combined interrupt @@ -217,18 +218,16 @@ properties: "#thermal-sensor-cells": const: 1 - description: - Number of cells required to uniquely identify the thermal sensors. Since - we have multiple sensors this is set to 1 required: - compatible - interrupts - interrupt-names - - "#thermal-sensor-cells" - "#qcom,sensors" allOf: + - $ref: thermal-sensor.yaml# + - if: properties: compatible: @@ -292,27 +291,21 @@ allOf: required: - reg -additionalProperties: false +unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - // Example msm9860 based SoC (ipq8064): - gcc: clock-controller { - - /* ... */ + thermal-sensor { + compatible = "qcom,ipq8064-tsens"; - tsens: thermal-sensor { - compatible = "qcom,ipq8064-tsens"; - - nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; - nvmem-cell-names = "calib", "calib_backup"; - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow"; + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; - #qcom,sensors = <11>; - #thermal-sensor-cells = <1>; - }; + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; }; - | @@ -349,66 +342,66 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> // Example 1 (legacy: for pre v1 IP): tsens1: thermal-sensor@4a9000 { - compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; - reg = <0x4a9000 0x1000>, /* TM */ - <0x4a8000 0x1000>; /* SROT */ + compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "calib", "calib_sel"; + nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; + nvmem-cell-names = "calib", "calib_sel"; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow"; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; - #qcom,sensors = <5>; - #thermal-sensor-cells = <1>; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; }; - | #include <dt-bindings/interrupt-controller/arm-gic.h> // Example 2 (for any platform containing v1 of the TSENS IP): tsens2: thermal-sensor@4a9000 { - compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow"; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; - #qcom,sensors = <10>; - #thermal-sensor-cells = <1>; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; }; - | #include <dt-bindings/interrupt-controller/arm-gic.h> // Example 3 (for any platform containing v2 of the TSENS IP): tsens3: thermal-sensor@c263000 { - compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0xc263000 0x1ff>, - <0xc222000 0x1ff>; + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0xc263000 0x1ff>, + <0xc222000 0x1ff>; - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; - #qcom,sensors = <13>; - #thermal-sensor-cells = <1>; + #qcom,sensors = <13>; + #thermal-sensor-cells = <1>; }; - | #include <dt-bindings/interrupt-controller/arm-gic.h> // Example 4 (for any IPQ8074 based SoC-s): tsens4: thermal-sensor@4a9000 { - compatible = "qcom,ipq8074-tsens"; - reg = <0x4a9000 0x1000>, - <0x4a8000 0x1000>; + compatible = "qcom,ipq8074-tsens"; + reg = <0x4a9000 0x1000>, + <0x4a8000 0x1000>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "combined"; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "combined"; - #qcom,sensors = <16>; - #thermal-sensor-cells = <1>; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml index d155d6799da6..1876fe9555d6 100644 --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml @@ -9,6 +9,8 @@ title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs maintainers: - Anson Huang <Anson.Huang@nxp.com> +$ref: thermal-sensor.yaml# + properties: compatible: description: | @@ -68,9 +70,8 @@ required: - interrupts - fsl,tmu-range - fsl,tmu-calibration - - '#thermal-sensor-cells' -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml index 6a81cb6e11bc..b6657d64cf3d 100644 --- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml @@ -15,6 +15,8 @@ description: maintainers: - Niklas Söderlund <niklas.soderlund@ragnatech.se> +$ref: thermal-sensor.yaml# + properties: compatible: enum: @@ -57,7 +59,6 @@ required: - clocks - power-domains - resets - - "#thermal-sensor-cells" if: properties: @@ -96,7 +97,7 @@ else: required: - interrupts -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -105,33 +106,33 @@ examples: #include <dt-bindings/power/r8a7795-sysc.h> tsc: thermal@e6198000 { - compatible = "renesas,r8a7795-thermal"; - reg = <0xe6198000 0x100>, - <0xe61a0000 0x100>, - <0xe61a8000 0x100>; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; + compatible = "renesas,r8a7795-thermal"; + reg = <0xe6198000 0x100>, + <0xe61a0000 0x100>, + <0xe61a8000 0x100>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; }; thermal-zones { - sensor_thermal: sensor-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; + sensor_thermal: sensor-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; }; + }; }; - | #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> @@ -139,14 +140,14 @@ examples: #include <dt-bindings/power/r8a779a0-sysc.h> tsc_r8a779a0: thermal@e6190000 { - compatible = "renesas,r8a779a0-thermal"; - reg = <0xe6190000 0x200>, - <0xe6198000 0x200>, - <0xe61a0000 0x200>, - <0xe61a8000 0x200>, - <0xe61b0000 0x200>; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 919>; - #thermal-sensor-cells = <1>; + compatible = "renesas,r8a779a0-thermal"; + reg = <0xe6190000 0x200>, + <0xe6198000 0x200>, + <0xe61a0000 0x200>, + <0xe61a8000 0x200>, + <0xe61b0000 0x200>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 919>; + #thermal-sensor-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml b/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml index 119998d10ff4..221a58d18cad 100644 --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml @@ -98,8 +98,8 @@ examples: # Example (non interrupt support) - | thermal@ffc48000 { - compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; - reg = <0xffc48000 0x38>; + compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; + reg = <0xffc48000 0x38>; }; # Example (interrupt support) @@ -109,12 +109,12 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> thermal@e61f0000 { - compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; - reg = <0xe61f0000 0x14>, <0xe61f0100 0x38>, - <0xe61f0200 0x38>, <0xe61f0300 0x38>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; - power-domains = <&pd_c5>; + compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; + reg = <0xe61f0000 0x14>, <0xe61f0100 0x38>, + <0xe61f0200 0x38>, <0xe61f0300 0x38>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; + power-domains = <&pd_c5>; }; # Example (with thermal-zone) @@ -124,32 +124,32 @@ examples: #include <dt-bindings/power/r8a7790-sysc.h> thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7790", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0xe61f0000 0x10>, <0xe61f0100 0x38>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; + compatible = "renesas,thermal-r8a7790", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0xe61f0000 0x10>, <0xe61f0100 0x38>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; }; thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; }; + cooling-maps { + }; + }; }; diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index 55f8ec0bec01..b717ea8261ca 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -9,6 +9,8 @@ title: Temperature Sensor ADC (TSADC) on Rockchip SoCs maintainers: - Heiko Stuebner <heiko@sntech.de> +$ref: thermal-sensor.yaml# + properties: compatible: enum: @@ -76,9 +78,8 @@ required: - clocks - clock-names - resets - - "#thermal-sensor-cells" -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/thermal/rzg2l-thermal.yaml b/Documentation/devicetree/bindings/thermal/rzg2l-thermal.yaml index 03f4b926e53c..136589f5adee 100644 --- a/Documentation/devicetree/bindings/thermal/rzg2l-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rzg2l-thermal.yaml @@ -13,6 +13,8 @@ description: maintainers: - Biju Das <biju.das.jz@bp.renesas.com> +$ref: thermal-sensor.yaml# + properties: compatible: items: @@ -43,36 +45,35 @@ required: - clocks - power-domains - resets - - "#thermal-sensor-cells" -additionalProperties: false +unevaluatedProperties: false examples: - | #include <dt-bindings/clock/r9a07g044-cpg.h> tsu: thermal@10059400 { - compatible = "renesas,r9a07g044-tsu", - "renesas,rzg2l-tsu"; - reg = <0x10059400 0x400>; - clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>; - resets = <&cpg R9A07G044_TSU_PRESETN>; - power-domains = <&cpg>; - #thermal-sensor-cells = <1>; + compatible = "renesas,r9a07g044-tsu", + "renesas,rzg2l-tsu"; + reg = <0x10059400 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>; + resets = <&cpg R9A07G044_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; }; thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsu 0>; - - trips { - sensor_crit: sensor-crit { - temperature = <125000>; - hysteresis = <1000>; - type = "critical"; - }; - }; + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; }; + }; }; diff --git a/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml b/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml index 1344df708e2d..29a08b0729ee 100644 --- a/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml @@ -61,7 +61,8 @@ properties: TRIMINFO at 0x10068000 contains data for TMU channel 2 minItems: 1 - '#thermal-sensor-cells': true + '#thermal-sensor-cells': + const: 0 vtmu-supply: description: The regulator node supplying voltage to TMU. diff --git a/Documentation/devicetree/bindings/thermal/socionext,uniphier-thermal.yaml b/Documentation/devicetree/bindings/thermal/socionext,uniphier-thermal.yaml index 6f975821fa5e..8210b7079721 100644 --- a/Documentation/devicetree/bindings/thermal/socionext,uniphier-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/socionext,uniphier-thermal.yaml @@ -14,6 +14,8 @@ description: | maintainers: - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> +$ref: thermal-sensor.yaml# + properties: compatible: enum: @@ -38,9 +40,8 @@ properties: required: - compatible - interrupts - - "#thermal-sensor-cells" -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/thermal/sprd-thermal.yaml b/Documentation/devicetree/bindings/thermal/sprd-thermal.yaml index 76aaa004c8ac..afa551f6185f 100644 --- a/Documentation/devicetree/bindings/thermal/sprd-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/sprd-thermal.yaml @@ -11,6 +11,8 @@ maintainers: - Baolin Wang <baolin.wang7@gmail.com> - Chunyan Zhang <zhang.lyra@gmail.com> +$ref: thermal-sensor.yaml# + properties: compatible: const: sprd,ums512-thermal @@ -77,35 +79,34 @@ required: - clock-names - nvmem-cells - nvmem-cell-names - - "#thermal-sensor-cells" - "#address-cells" - "#size-cells" -additionalProperties: false +unevaluatedProperties: false examples: - | - ap_thm0: thermal@32200000 { - compatible = "sprd,ums512-thermal"; - reg = <0x32200000 0x10000>; - clock-names = "enable"; - clocks = <&aonapb_gate 32>; - #thermal-sensor-cells = <1>; - nvmem-cells = <&thm0_sign>, <&thm0_ratio>; - nvmem-cell-names = "thm_sign_cal", "thm_ratio_cal"; - #address-cells = <1>; - #size-cells = <0>; - - prometheus-sensor@0 { - reg = <0>; - nvmem-cells = <&thm0_sen0>; - nvmem-cell-names = "sen_delta_cal"; - }; - - ank-sensor@1 { - reg = <1>; - nvmem-cells = <&thm0_sen1>; - nvmem-cell-names = "sen_delta_cal"; - }; + thermal@32200000 { + compatible = "sprd,ums512-thermal"; + reg = <0x32200000 0x10000>; + clock-names = "enable"; + clocks = <&aonapb_gate 32>; + #thermal-sensor-cells = <1>; + nvmem-cells = <&thm0_sign>, <&thm0_ratio>; + nvmem-cell-names = "thm_sign_cal", "thm_ratio_cal"; + #address-cells = <1>; + #size-cells = <0>; + + prometheus-sensor@0 { + reg = <0>; + nvmem-cells = <&thm0_sen0>; + nvmem-cell-names = "sen_delta_cal"; + }; + + ank-sensor@1 { + reg = <1>; + nvmem-cells = <&thm0_sen1>; + nvmem-cell-names = "sen_delta_cal"; }; + }; ... diff --git a/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml b/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml index ab043084f667..1c01a80a0cdd 100644 --- a/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml @@ -9,6 +9,8 @@ title: STMicroelectronics STM32 digital thermal sensor (DTS) maintainers: - Pascal Paillet <p.paillet@foss.st.com> +$ref: thermal-sensor.yaml# + properties: compatible: const: st,stm32-thermal @@ -30,14 +32,13 @@ properties: const: 0 required: - - "#thermal-sensor-cells" - compatible - reg - interrupts - clocks - clock-names -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/thermal/thermal-zones.yaml b/Documentation/devicetree/bindings/thermal/thermal-zones.yaml index 68398e7e8655..0f435be1dbd8 100644 --- a/Documentation/devicetree/bindings/thermal/thermal-zones.yaml +++ b/Documentation/devicetree/bindings/thermal/thermal-zones.yaml @@ -49,7 +49,10 @@ properties: to take when the temperature crosses those thresholds. patternProperties: - "^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$": + # Node name is limited in size due to Linux kernel requirements - 19 + # characters in total (see THERMAL_NAME_LENGTH, including terminating NUL + # byte): + "^[a-zA-Z][a-zA-Z0-9\\-]{1,10}-thermal$": type: object description: Each thermal zone node contains information about how frequently it @@ -229,7 +232,6 @@ patternProperties: required: - thermal-sensors - - trips additionalProperties: false diff --git a/Documentation/devicetree/bindings/thermal/ti,am654-thermal.yaml b/Documentation/devicetree/bindings/thermal/ti,am654-thermal.yaml index 7ed0abe9290f..c123d9070525 100644 --- a/Documentation/devicetree/bindings/thermal/ti,am654-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/ti,am654-thermal.yaml @@ -9,6 +9,8 @@ title: Texas Instruments AM654 VTM (DTS) maintainers: - Keerthy <j-keerthy@ti.com> +$ref: thermal-sensor.yaml# + properties: compatible: const: ti,am654-vtm @@ -26,9 +28,8 @@ required: - compatible - reg - power-domains - - "#thermal-sensor-cells" -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -46,11 +47,11 @@ examples: thermal-sensors = <&vtm0 0>; trips { - mpu0_crit: mpu0_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; + mpu0_crit: mpu0_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; }; }; ... diff --git a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml index 171b3622ed84..82b77b9795a3 100644 --- a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml @@ -22,6 +22,8 @@ description: | Temp(C) = (-9.2627e-12) * x^4 + (6.0373e-08) * x^3 + \ (-1.7058e-04) * x^2 + (3.2512e-01) * x + (-4.9003e+01) +$ref: thermal-sensor.yaml# + properties: compatible: enum: @@ -64,9 +66,8 @@ required: - compatible - reg - power-domains - - "#thermal-sensor-cells" -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/timer/realtek,otto-timer.yaml b/Documentation/devicetree/bindings/timer/realtek,otto-timer.yaml new file mode 100644 index 000000000000..7b6ec2c69484 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/realtek,otto-timer.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/realtek,otto-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek Otto SoCs Timer/Counter + +description: + Realtek SoCs support a number of timers/counters. These are used + as a per CPU clock event generator and an overall CPU clocksource. + +maintainers: + - Chris Packham <chris.packham@alliedtelesis.co.nz> + +properties: + $nodename: + pattern: "^timer@[0-9a-f]+$" + + compatible: + items: + - enum: + - realtek,rtl9302-timer + - const: realtek,otto-timer + + reg: + items: + - description: timer0 registers + - description: timer1 registers + - description: timer2 registers + - description: timer3 registers + - description: timer4 registers + + clocks: + maxItems: 1 + + interrupts: + items: + - description: timer0 interrupt + - description: timer1 interrupt + - description: timer2 interrupt + - description: timer3 interrupt + - description: timer4 interrupt + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + timer@3200 { + compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, + <0x3230 0x10>, <0x3240 0x10>; + + interrupt-parent = <&intc>; + interrupts = <7>, <8>, <9>, <10>, <11>; + clocks = <&lx_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml index 360a5cf1ae9c..b6dd98d956f3 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml @@ -21,13 +21,24 @@ properties: compatible: items: - enum: + - renesas,tmu-r8a73a4 # R-Mobile APE6 - renesas,tmu-r8a7740 # R-Mobile A1 + - renesas,tmu-r8a7742 # RZ/G1H + - renesas,tmu-r8a7743 # RZ/G1M + - renesas,tmu-r8a7744 # RZ/G1N + - renesas,tmu-r8a7745 # RZ/G1E + - renesas,tmu-r8a77470 # RZ/G1C - renesas,tmu-r8a774a1 # RZ/G2M - renesas,tmu-r8a774b1 # RZ/G2N - renesas,tmu-r8a774c0 # RZ/G2E - renesas,tmu-r8a774e1 # RZ/G2H - renesas,tmu-r8a7778 # R-Car M1A - renesas,tmu-r8a7779 # R-Car H1 + - renesas,tmu-r8a7790 # R-Car H2 + - renesas,tmu-r8a7791 # R-Car M2-W + - renesas,tmu-r8a7792 # R-Car V2H + - renesas,tmu-r8a7793 # R-Car M2-N + - renesas,tmu-r8a7794 # R-Car E2 - renesas,tmu-r8a7795 # R-Car H3 - renesas,tmu-r8a7796 # R-Car M3-W - renesas,tmu-r8a77961 # R-Car M3-W+ @@ -94,6 +105,7 @@ if: compatible: contains: enum: + - renesas,tmu-r8a73a4 - renesas,tmu-r8a7740 - renesas,tmu-r8a7778 - renesas,tmu-r8a7779 diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index fced6f2d8ecb..b42d43d2de48 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -40,6 +40,7 @@ properties: - allwinner,sun20i-d1-clint - sophgo,cv1800b-clint - sophgo,cv1812h-clint + - sophgo,sg2002-clint - thead,th1520-clint - const: thead,c900-clint - items: diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 0a419453d183..03e290cb65c3 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -168,6 +168,8 @@ properties: - isil,isl69269 # Intersil ISL76682 Ambient Light Sensor - isil,isl76682 + # JEDEC JESD300 (SPD5118) Hub and Serial Presence Detect + - jedec,spd5118 # Linear Technology LTC2488 - lineartechnology,ltc2488 # 5 Bit Programmable, Pulse-Width Modulator @@ -286,14 +288,22 @@ properties: - mps,mp2857 # Monolithic Power Systems Inc. multi-phase controller mp2888 - mps,mp2888 + # Monolithic Power Systems Inc. multi-phase controller mp2891 + - mps,mp2891 # Monolithic Power Systems Inc. multi-phase controller mp2971 - mps,mp2971 # Monolithic Power Systems Inc. multi-phase controller mp2973 - mps,mp2973 # Monolithic Power Systems Inc. multi-phase controller mp2975 - mps,mp2975 + # Monolithic Power Systems Inc. multi-phase controller mp2993 + - mps,mp2993 + # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5920 + - mps,mp5920 # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990 - mps,mp5990 + # Monolithic Power Systems Inc. digital step-down converter mp9941 + - mps,mp9941 # Monolithic Power Systems Inc. synchronous step-down converter mpq8785 - mps,mpq8785 # Temperature sensor with integrated fan control diff --git a/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml b/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml index 0874fc21f66f..6577a61cc075 100644 --- a/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml +++ b/Documentation/devicetree/bindings/usb/realtek,rts5411.yaml @@ -65,6 +65,7 @@ patternProperties: description: The hard wired USB devices type: object $ref: /schemas/usb/usb-device.yaml + additionalProperties: true required: - peer-hub diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index fbf47f0bacf1..87ec6772b2d4 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -338,6 +338,8 @@ patternProperties: description: Czech Technical University in Prague "^cubietech,.*": description: Cubietech, Ltd. + "^cudy,.*": + description: Shenzhen Cudy Technology Co., Ltd. "^cui,.*": description: CUI Devices "^cypress,.*": @@ -394,6 +396,8 @@ patternProperties: description: DPTechnics "^dragino,.*": description: Dragino Technology Co., Limited + "^dream,.*": + description: Dream Property GmbH "^ds,.*": description: DaSheng, Inc. "^dserve,.*": @@ -995,6 +999,8 @@ patternProperties: description: MYIR Tech Limited "^national,.*": description: National Semiconductor + "^neardi,.*": + description: Shanghai Neardi Technology Co., Ltd. "^nec,.*": description: NEC LCD Technologies, Ltd. "^neonode,.*": @@ -1082,6 +1088,8 @@ patternProperties: description: OpenPandora GmbH "^openrisc,.*": description: OpenRISC.io + "^openwrt,.*": + description: OpenWrt "^option,.*": description: Option NV "^oranth,.*": @@ -1254,6 +1262,8 @@ patternProperties: description: Smart Battery System "^schindler,.*": description: Schindler + "^schneider,.*": + description: Schneider Electric "^seagate,.*": description: Seagate Technology PLC "^seeed,.*": |