diff options
| author | Ben Widawsky <ben.widawsky@intel.com> | 2022-02-02 20:02:06 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-08 22:57:32 -0800 |
| commit | 9b71e1c9c3aaae5079f5e267785b6f035c5f23da (patch) | |
| tree | ee0ac1c881f2a714a7860c7251fd26c4cdd6a0ac /usr | |
| parent | 8aea0ef19fde030f983aba0e7ec5bcf10880a6fe (diff) | |
cxl/core/port: Add endpoint decoders
Recall that a CXL Port is any object that publishes a CXL HDM Decoder
Capability structure. That is Host Bridge and Switches that have been
enabled so far. Now, add decoder support to the 'endpoint' CXL Ports
registered by the cxl_mem driver. They mostly share the same enumeration
as Bridges and Switches, but witout a target list. The target of
endpoint decode is device-internal DPA space, not another downstream
port.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
[djbw: clarify changelog, hookup enumeration in the port driver]
Link: https://lore.kernel.org/r/164386092069.765089.14895687988217608642.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'usr')
0 files changed, 0 insertions, 0 deletions