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authorRasmus Villemoes <linux@rasmusvillemoes.dk>2019-11-28 15:55:54 +0100
committerLi Yang <leoyang.li@nxp.com>2019-12-09 13:57:45 -0600
commit5a35435ef4e6e4bd2aabd6706b146b298a9cffe5 (patch)
tree084c6245492e5de9273330d31c3527b4316d0fb1 /lib/ratelimit.c
parent8d70df8b88a2c365a198003f2ae0df19d0825b91 (diff)
soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE
There are also PPC64, ARM and ARM64 based SOCs with a QUICC Engine, and the core QE code as well as net/wan/fsl_ucc_hdlc and tty/serial/ucc_uart has now been modified to not rely on ppcisms. So extend the architectures that can select QUICC_ENGINE, and add the rather modest requirements of OF && HAS_IOMEM. The core code as well as the ucc_uart driver has been tested on an LS1021A (arm), and it has also been tested that the QE code still works on an mpc8309 (ppc). Qiang Zhao has tested that the QE-HDLC code that gets enabled with this works on ARM64. Reviewed-by: Timur Tabi <timur@kernel.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Li Yang <leoyang.li@nxp.com>
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