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authorArnd Bergmann <arnd@arndb.de>2020-11-30 17:22:02 +0100
committerArnd Bergmann <arnd@arndb.de>2020-11-30 17:22:03 +0100
commitbbecede458d042a5b71d6f10eedd471615d9ee6c (patch)
tree916ea9067c7eff83468ba3ddfebcc7967eda661b /include/dt-bindings
parente9ab9c337beecd41f4cc98d536cd6299264d818f (diff)
parentcc6576029aedc79ce87b9fcb22cbd396d47f2852 (diff)
Merge tag 'v5.10-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers
power-domains: - add support for new power domain driver. - add support for mt8183 and mt8192 devapc: - add support for the devapc device found on mt6779 to identify of malicious bus accesses from a controller to a device mmsys: - move DDP routing IDs into the driver cmdq: - drop timeout handler support as not usefull scpsys: - print warning on theoretical error * tag 'v5.10-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (21 commits) soc: mediatek: mmsys: Use devm_platform_ioremap_resource() soc / drm: mediatek: Move DDP component defines into mtk-mmsys.h soc: mediatek: add mt6779 devapc driver dt-bindings: devapc: add bindings for mtk-devapc soc / drm: mediatek: cmdq: Remove timeout handler in helper function soc: mediatek: pm-domains: Add support for mt8192 soc: mediatek: pm-domains: Add default power off flag soc: mediatek: pm-domains: Add support for mt8183 soc: mediatek: pm-domains: Allow bus protection to ignore clear ack soc: mediatek: pm-domains: Add subsystem clocks soc: mediatek: pm-domains: Add extra sram control soc: mediatek: pm-domains: Add SMI block as bus protection block soc: mediatek: pm_domains: Make bus protection generic soc: mediatek: pm-domains: Add bus protection protocol soc: mediatek: Add MediaTek SCPSYS power domains dt-bindings: power: Add MT8192 power domains dt-bindings: power: Add MT8183 power domains dt-bindings: power: Add bindings for the Mediatek SCPSYS power domains controller mfd: syscon: Add syscon_regmap_lookup_by_phandle_optional() function. MAINTAINERS: change mediatek wiki page ... Link: https://lore.kernel.org/r/b03fe343-e183-c6f3-f2dc-4c58aae3146b@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/power/mt8183-power.h26
-rw-r--r--include/dt-bindings/power/mt8192-power.h32
2 files changed, 58 insertions, 0 deletions
diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h
new file mode 100644
index 000000000000..d1ab387ba8c7
--- /dev/null
+++ b/include/dt-bindings/power/mt8183-power.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8183_POWER_DOMAIN_AUDIO 0
+#define MT8183_POWER_DOMAIN_CONN 1
+#define MT8183_POWER_DOMAIN_MFG_ASYNC 2
+#define MT8183_POWER_DOMAIN_MFG 3
+#define MT8183_POWER_DOMAIN_MFG_CORE0 4
+#define MT8183_POWER_DOMAIN_MFG_CORE1 5
+#define MT8183_POWER_DOMAIN_MFG_2D 6
+#define MT8183_POWER_DOMAIN_DISP 7
+#define MT8183_POWER_DOMAIN_CAM 8
+#define MT8183_POWER_DOMAIN_ISP 9
+#define MT8183_POWER_DOMAIN_VDEC 10
+#define MT8183_POWER_DOMAIN_VENC 11
+#define MT8183_POWER_DOMAIN_VPU_TOP 12
+#define MT8183_POWER_DOMAIN_VPU_CORE0 13
+#define MT8183_POWER_DOMAIN_VPU_CORE1 14
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings/power/mt8192-power.h
new file mode 100644
index 000000000000..4eaa53d7270a
--- /dev/null
+++ b/include/dt-bindings/power/mt8192-power.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8192_POWER_H
+#define _DT_BINDINGS_POWER_MT8192_POWER_H
+
+#define MT8192_POWER_DOMAIN_AUDIO 0
+#define MT8192_POWER_DOMAIN_CONN 1
+#define MT8192_POWER_DOMAIN_MFG0 2
+#define MT8192_POWER_DOMAIN_MFG1 3
+#define MT8192_POWER_DOMAIN_MFG2 4
+#define MT8192_POWER_DOMAIN_MFG3 5
+#define MT8192_POWER_DOMAIN_MFG4 6
+#define MT8192_POWER_DOMAIN_MFG5 7
+#define MT8192_POWER_DOMAIN_MFG6 8
+#define MT8192_POWER_DOMAIN_DISP 9
+#define MT8192_POWER_DOMAIN_IPE 10
+#define MT8192_POWER_DOMAIN_ISP 11
+#define MT8192_POWER_DOMAIN_ISP2 12
+#define MT8192_POWER_DOMAIN_MDP 13
+#define MT8192_POWER_DOMAIN_VENC 14
+#define MT8192_POWER_DOMAIN_VDEC 15
+#define MT8192_POWER_DOMAIN_VDEC2 16
+#define MT8192_POWER_DOMAIN_CAM 17
+#define MT8192_POWER_DOMAIN_CAM_RAWA 18
+#define MT8192_POWER_DOMAIN_CAM_RAWB 19
+#define MT8192_POWER_DOMAIN_CAM_RAWC 20
+
+#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */