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authorSai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>2021-04-15 16:43:12 +0530
committerLinus Walleij <linus.walleij@linaro.org>2021-04-22 01:58:59 +0200
commit1dccb5ec01231156b06420633e3eedef95b17eac (patch)
tree74c501f43356aae91339c0317eec2147070c66a8 /include/dt-bindings
parent11f054c114f261ae04fc0b2ad9c1d4e1becd8b14 (diff)
dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver
Adding documentation and dt-bindings file which contains MIO pin configuration defines for Xilinx ZynqMP pinctrl driver. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1618485193-5403-3-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/pinctrl/pinctrl-zynqmp.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
new file mode 100644
index 000000000000..cdb215734bdf
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * MIO pin configuration defines for Xilinx ZynqMP
+ *
+ * Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
+#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
+
+/* Bit value for different voltage levels */
+#define IO_STANDARD_LVCMOS33 0
+#define IO_STANDARD_LVCMOS18 1
+
+/* Bit values for Slew Rates */
+#define SLEW_RATE_FAST 0
+#define SLEW_RATE_SLOW 1
+
+#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */